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master
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protected
71834520
·
re-routing atca clocks. compilingOK
·
Sep 12, 2023
master_board
2cc784e6
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Master only FW. Clock is local
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Sep 01, 2023
integral_32
922ffd53
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Update README.md
·
Apr 07, 2023
atca_slave
b98b843e
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Forcing board board to be atca slave
·
Dec 12, 2022
vivado_2022.1
963e8729
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Changed EO correction parameters. 18 bit raw data. FW Version: 0x02020013
·
Oct 11, 2022
slot_id_0xCE
0252ba0c
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Graching Slot Id 0xCE. FWv 0x02020011
·
Dec 17, 2021
fifo_reset
051b58dd
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Changing Internal calcultions to Double Float
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Nov 18, 2021
dual_fifo
f0870862
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Float calc values, testing again...
·
Nov 17, 2021
change_defs
a0f20b7c
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Debuging Float calc valuesgcs
·
Nov 15, 2021
Shift_reg16_mod
9ac0281f
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Deleted bit file
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Oct 01, 2021
Shift_reg16
108a9387
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Compiled non-project mode. ADC DDR version
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Oct 01, 2021
v2.0_Testing
a14fd99c
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changed RTM outputs
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Jul 27, 2021
xdma
31e3302b
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Implemented F interlock signals TS:1626263305
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Jul 14, 2021
Interlock_calc
fb794824
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dechopping, Int , Mult 1 channel
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Oct 30, 2020
32channels16bit
5c7432c4
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4MBytes MAx DMA buffers, mcs working
·
Sep 29, 2020
implementing_dual_dma
6caac81d
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Data CH0 tested in kc705
·
Sep 04, 2019
kc705-fake
0c2d0947
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New Header/Footer, dmaSize: 16512
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Jul 08, 2019
vivado_18.3
52d3fac8
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changed driver printfs
·
Jun 06, 2019
adc_sr
1b1c5a10
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i not getting data
·
Jun 05, 2019