Commit 6caac81d authored by Bernardo Carvalho's avatar Bernardo Carvalho
Browse files

Data CH0 tested in kc705

parent 26d4ba66
......@@ -32,6 +32,9 @@
int bind_to_cpu(int core_id);
void get_pckt_adc_data(int32_t *pAdcData, DMA_PCKT *pPckDma);
void get_rt_pckt_adc_data(int32_t *pAdcData, DMACH1_PCKT *pPckDma);
unsigned int get_pckt_head_magic(DMA_PCKT *pPdma);
unsigned int get_pckt_foot_magic(DMA_PCKT *pPdma);
uint64_t get_sample_cnt(SAMPLE *pSamp);
int atca_mimo_v2_stop_acq(int fd);
unsigned long int time_interval_us(struct timeval *tstart,
struct timeval *tend);
......
......@@ -41,7 +41,7 @@ typedef struct _HEAD_FOOT_FLDS {
} HEAD_FOOT_FLDS;
typedef struct _SAMPLE {
DATA_FLDS channel[ADC_CHANNELS];
volatile DATA_FLDS channel[ADC_CHANNELS];
} SAMPLE;
typedef struct _HEAD_SAMPLE {
......@@ -58,7 +58,7 @@ typedef struct _FOOT_SAMPLE {
typedef struct _DMA_PCKT {
// volatile HEAD_SAMPLE hsamp;
volatile SAMPLE samp[PCK_N_SAMPLES];
SAMPLE samp[PCK_N_SAMPLES];
// volatile FOOT_SAMPLE fsamp;
} DMA_PCKT;
......
......@@ -82,10 +82,11 @@ int bind_to_cpu(int core_id) {
}
int atca_mimo_v2_stop_acq(int fd) {
int max_buf_count = ioctl(fd, ATCA_PCIE_IOCT_ACQ_DISABLE);
int rc = ioctl(fd, ATCA_PCIE_IOCT_STREAM_DISABLE);
/*int rc = */
ioctl(fd, ATCA_PCIE_IOCT_STREAM_DISABLE);
// PDEBUG("ACQ Stopped, FPGA Status: 0x%.8X, max buff_count: %d \n", tmp,
// max_buf_count);
return rc;
return max_buf_count;
}
/*unsigned long int time_interval_us(tstart, tend) struct timespec *tstart,
* *tend;*/
......@@ -101,93 +102,121 @@ void get_rt_pckt_adc_data(int32_t *pAdcData, DMACH1_PCKT *pPdma) {
for (int j = 0; j < ADC_CHANNELS; j++)
*pAdcData++ = pPdma->adc_decim_data.channel[j].adc_data;
}
void get_pckt_adc_data(int32_t *pAdcData, DMA_PCKT *pPdma) {
int j, sdata;
unsigned int udata20bit, uval;
struct {
signed int x : 20;
} s; // structure for sign extend
/*Packet Header */
/**pAdcData++ = pPdma->hsamp.time_cnt;*/
udata20bit = pPdma->hsamp.channel[0].data_byte;
udata20bit |= pPdma->hsamp.channel[1].data_byte << 8;
udata20bit |= pPdma->hsamp.channel[2].data_byte << 16;
sdata = s.x = udata20bit;
*pAdcData++ = sdata;
udata20bit = pPdma->hsamp.channel[3].data_byte;
udata20bit |= pPdma->hsamp.channel[4].data_byte << 8;
udata20bit |= pPdma->hsamp.channel[5].data_byte << 16;
sdata = s.x = udata20bit;
*pAdcData++ = sdata;
udata20bit = pPdma->hsamp.channel[6].data_byte;
udata20bit |= pPdma->hsamp.channel[7].data_byte << 8;
udata20bit |= pPdma->hsamp.channel[8].data_byte << 16;
sdata = s.x = udata20bit;
*pAdcData++ = sdata;
uval = pPdma->hsamp.channel[9].data_byte;
udata20bit = uval; // pPdma->hsamp.channel[9].data_byte;
udata20bit |= pPdma->hsamp.channel[10].data_byte << 8;
udata20bit |= pPdma->hsamp.channel[11].data_byte << 16;
sdata = s.x = udata20bit;
*pAdcData++ = sdata;
/**pAdcData++ = pPdma->hsamp.header.buf_num;*/
/*for (j = 2; j < 4; j++)*/
/**pAdcData++ = 0;*/
for (j = 0; j < ADC_CHANNELS - 4; j++)
*pAdcData++ = pPdma->hsamp.channel[j].adc_data;
void get_pckt_adc_data(int32_t *pAdcData, DMA_PCKT *pPdma) {
/*Normal samples*/
for (int i = 0; i < PCK_N_SAMPLES - 2; i++) {
/*
udata20bit |= pdma[buf_num].samp[i].channel[4].data_byte;
udata20bit |= pdma[buf_num].samp[i].channel[5].data_byte << 8;
udata20bit |= pdma[buf_num].samp[i].channel[6].data_byte << 16;
udata20bit |= pdma[buf_num].samp[i].channel[7].data_byte << 24;
*pAdcData++ = udata20bit;
*/
for (j = 0; j < ADC_CHANNELS; j++)
for (int i = 0; i < PCK_N_SAMPLES; i++) {
for (int j = 0; j < ADC_CHANNELS; j++)
*pAdcData++ = pPdma->samp[i].channel[j].adc_data;
}
}
unsigned int get_pckt_head_magic(DMA_PCKT *pPdma) {
unsigned int uval = 0;
for (int i = 0; i < 4; i++) {
uval |= pPdma->samp[0].channel[i].data_byte << (i * 8);
}
return uval;
}
unsigned int get_pckt_foot_magic(DMA_PCKT *pPdma) {
unsigned int uval = 0;
for (int i = 0; i < 4; i++) {
uval |= (pPdma->samp[PCK_N_SAMPLES - 1].channel[i].data_byte) << (i * 8);
}
return uval;
}
uint64_t get_sample_cnt(SAMPLE *pSamp) {
uint64_t uval = 0;
for (int i = 0; i < 8; i++) {
uval |= (pSamp->channel[8 + i].data_byte) << (i * 8);
}
return uval;
}
/*void get_pckt_adc_data(int32_t *pAdcData, DMA_PCKT *pPdma) {*/
/*int j, sdata;*/
/*unsigned int udata20bit, uval;*/
/*struct {*/
/*signed int x : 20;*/
/*} s; // structure for sign extend*/
/*[>Packet Header <]*/
/*[>*pAdcData++ = pPdma->hsamp.time_cnt;<]*/
/*udata20bit = pPdma->hsamp.channel[0].data_byte;*/
/*udata20bit |= pPdma->hsamp.channel[1].data_byte << 8;*/
/*udata20bit |= pPdma->hsamp.channel[2].data_byte << 16;*/
/*sdata = s.x = udata20bit;*/
/**pAdcData++ = sdata;*/
/*udata20bit = pPdma->hsamp.channel[3].data_byte;*/
/*udata20bit |= pPdma->hsamp.channel[4].data_byte << 8;*/
/*udata20bit |= pPdma->hsamp.channel[5].data_byte << 16;*/
/*sdata = s.x = udata20bit;*/
/**pAdcData++ = sdata;*/
/*udata20bit = pPdma->hsamp.channel[6].data_byte;*/
/*udata20bit |= pPdma->hsamp.channel[7].data_byte << 8;*/
/*udata20bit |= pPdma->hsamp.channel[8].data_byte << 16;*/
/*sdata = s.x = udata20bit;*/
/**pAdcData++ = sdata;*/
/*uval = pPdma->hsamp.channel[9].data_byte;*/
/*udata20bit = uval; // pPdma->hsamp.channel[9].data_byte;*/
/*udata20bit |= pPdma->hsamp.channel[10].data_byte << 8;*/
/*udata20bit |= pPdma->hsamp.channel[11].data_byte << 16;*/
/*sdata = s.x = udata20bit;*/
/**pAdcData++ = sdata;*/
/*[>*pAdcData++ = pPdma->hsamp.header.buf_num;<]*/
/*[>for (j = 2; j < 4; j++)<]*/
/*[>*pAdcData++ = 0;<]*/
/*for (j = 0; j < ADC_CHANNELS - 4; j++)*/
/**pAdcData++ = pPdma->hsamp.channel[j].adc_data;*/
/*Packet Footer */
for (j = 0; j < ADC_CHANNELS - 4; j++)
*pAdcData++ = pPdma->fsamp.channel[j].adc_data;
/*[>Normal samples<]*/
/*for (int i = 0; i < PCK_N_SAMPLES - 2; i++) {*/
/*/**/
/*udata20bit |= pdma[buf_num].samp[i].channel[4].data_byte;*/
/*udata20bit |= pdma[buf_num].samp[i].channel[5].data_byte << 8;*/
/*udata20bit |= pdma[buf_num].samp[i].channel[6].data_byte << 16;*/
/*udata20bit |= pdma[buf_num].samp[i].channel[7].data_byte << 24;*/
/**pAdcData++ = udata20bit;*/
/*for (j = 0; j < ADC_CHANNELS; j++)*/
/**pAdcData++ = pPdma->samp[i].channel[j].adc_data;*/
/*}*/
udata20bit = pPdma->fsamp.channel[16].data_byte;
udata20bit |= pPdma->fsamp.channel[17].data_byte << 8;
udata20bit |= pPdma->fsamp.channel[18].data_byte << 16;
*pAdcData++ = s.x = udata20bit;
udata20bit = pPdma->fsamp.channel[19].data_byte;
udata20bit |= pPdma->fsamp.channel[20].data_byte << 8;
udata20bit |= pPdma->fsamp.channel[21].data_byte << 16;
*pAdcData++ = s.x = udata20bit; // sdata;
udata20bit = pPdma->fsamp.channel[22].data_byte;
udata20bit |= pPdma->fsamp.channel[23].data_byte << 8;
udata20bit |= pPdma->fsamp.channel[24].data_byte << 16;
*pAdcData++ = s.x = udata20bit;
udata20bit = pPdma->fsamp.channel[25].data_byte;
udata20bit |= pPdma->fsamp.channel[26].data_byte << 8;
udata20bit |= pPdma->fsamp.channel[27].data_byte << 16;
*pAdcData++ = s.x = udata20bit;
/*
uval = pPdma->fsamp.channel[25].data_byte;
udata20bit = uval; // pPdma->hsamp.channel[9].data_byte;
printf("uval 0x%X ", uval);
udata20bit = pPdma->fsamp.channel[9].data_byte;
uval = pPdma->fsamp.channel[26].data_byte << 8;
udata20bit |= uval; // pPdma->fsamp.channel[10].data_byte << 8;
printf(" 0x%X ", uval);
uval = pPdma->fsamp.channel[27].data_byte << 16;
udata20bit |= uval; // pPdma->fsamp.channel[11].data_byte << 16;
printf(" 0x%X ", uval);
sdata = s.x = udata20bit;
printf("sdata 0x%X\n", sdata);
*pAdcData++ = sdata;
*/
/*for (j = 0; j < 2; j++)
*pAdcData++ = 0;
*pAdcData++ = pPdma->fsamp.time_cnt;
*pAdcData++ = pPdma->fsamp.footer.buf_num;
*/
return;
}
/*[>Packet Footer <]*/
/*for (j = 0; j < ADC_CHANNELS - 4; j++)*/
/**pAdcData++ = pPdma->fsamp.channel[j].adc_data;*/
/*udata20bit = pPdma->fsamp.channel[16].data_byte;*/
/*udata20bit |= pPdma->fsamp.channel[17].data_byte << 8;*/
/*udata20bit |= pPdma->fsamp.channel[18].data_byte << 16;*/
/**pAdcData++ = s.x = udata20bit;*/
/*udata20bit = pPdma->fsamp.channel[19].data_byte;*/
/*udata20bit |= pPdma->fsamp.channel[20].data_byte << 8;*/
/*udata20bit |= pPdma->fsamp.channel[21].data_byte << 16;*/
/**pAdcData++ = s.x = udata20bit; // sdata;*/
/*udata20bit = pPdma->fsamp.channel[22].data_byte;*/
/*udata20bit |= pPdma->fsamp.channel[23].data_byte << 8;*/
/*udata20bit |= pPdma->fsamp.channel[24].data_byte << 16;*/
/**pAdcData++ = s.x = udata20bit;*/
/*udata20bit = pPdma->fsamp.channel[25].data_byte;*/
/*udata20bit |= pPdma->fsamp.channel[26].data_byte << 8;*/
/*udata20bit |= pPdma->fsamp.channel[27].data_byte << 16;*/
/**pAdcData++ = s.x = udata20bit;*/
/**/
/*uval = pPdma->fsamp.channel[25].data_byte;*/
/*udata20bit = uval; // pPdma->hsamp.channel[9].data_byte;*/
/*printf("uval 0x%X ", uval);*/
/*udata20bit = pPdma->fsamp.channel[9].data_byte;*/
/*uval = pPdma->fsamp.channel[26].data_byte << 8;*/
/*udata20bit |= uval; // pPdma->fsamp.channel[10].data_byte << 8;*/
/*printf(" 0x%X ", uval);*/
/*uval = pPdma->fsamp.channel[27].data_byte << 16;*/
/*udata20bit |= uval; // pPdma->fsamp.channel[11].data_byte << 16;*/
/*printf(" 0x%X ", uval);*/
/*sdata = s.x = udata20bit;*/
/*printf("sdata 0x%X\n", sdata);*/
/**pAdcData++ = sdata;*/
/**/
/*for (j = 0; j < 2; j++)
*pAdcData++ = 0;
*pAdcData++ = pPdma->fsamp.time_cnt;
*pAdcData++ = pPdma->fsamp.footer.buf_num;
*/
/*return;*/
/*}*/
......@@ -175,15 +175,16 @@ int main(int argc, char **argv) {
rc = read(fd, dmaBuff, dmaSize); // loop read.
memcpy(pAdcDataWr, dmaBuff, dmaSize);
pAdcDataWr += dmaSize / sizeof(int32_t);
header = pdma->samp[0].channel[4].data_byte;
footer = pdma->samp[PCK_N_SAMPLES - 1].channel[20].data_byte;
header = get_sample_cnt(&pdma->samp[0]); //.channel[8].data_byte;
footer = pdma->samp[PCK_N_SAMPLES - 1].channel[24].data_byte;
/*footer = pdma->fsamp.time_cnt;*/
/*footer = pdma->fsamp.time_cnt;*/
magic = pdma->samp[0].channel[0].data_byte;
/*magic = pdma->samp[0].channel[0].data_byte;*/
magic = get_pckt_head_magic(pdma);
/*magic = pdma->hsamp.header.magic;*/
fmagic = pdma->samp[PCK_N_SAMPLES - 1].channel[16].data_byte;
fmagic = get_pckt_foot_magic(pdma);
/*fmagic = pdma->samp[PCK_N_SAMPLES - 1].channel[16].data_byte;*/
/*= pdma->fsamp.footer.magic;*/
if (magic != 0x54320000) {
if (magic != 0x54310100) {
printf("Err pckt: %d, magic: 0x%X\n", i, magic);
Run = 0;
}
......
No preview for this file type
......@@ -145,7 +145,7 @@ module PIO_EP #(
wire [7:0] dma_status;
//wire [5:0] dma_payload_tx;
wire [63:0] dma_pkt_cnt;
//wire [63:0] dma_pkt_cnt;
wire [31:0] host_addr_tx;
(* mark_debug="yes" *) wire [63:0] dma_data;
wire dma_tlp_req;
......@@ -331,7 +331,7 @@ module PIO_EP #(
.tlp_req(dma_tlp_req), //O
.dma_tlp_compl_done(dma_tlp_compl_done), //I
.clk_2_cnt(clk_2_cnt), // I
.dma_pkt_cnt(dma_pkt_cnt), // O
//.dma_pkt_cnt(dma_pkt_cnt), // O
.adc_data_clk(clk_100), // I
.data_in_ch0(data_ch0), // I
.data_valid_ch0(data_valid_ch0), // I
......
......@@ -102,10 +102,10 @@ module data_producer #(
reg data_vld_ch0_r, data_vld_ch1_r;
assign data_valid_ch0 = data_vld_ch0_r;
assign data_valid_ch1 = data_vld_ch1_r;
reg [63 :0] cnt_pckt_r, cnt_ch1_pckt_r, cnt_ch1_foot_r;
reg [63 :0] cnt_pckt_ch0_r, cnt_pckt_ch1_r, cnt_ch1_foot_r;
reg [PKT_SAMPLES_WIDTH -1 :0] cnt_sample_r;
reg [7:0] cnt_decim_ch1_r;
(* mark_debug="yes" *) wire [7:0] cnt_data_i = cnt_pckt_r[7:0];
(* mark_debug="yes" *) wire [7:0] cnt_data_i = cnt_pckt_ch0_r[7:0];
reg [DMA_FIFO_DATA_IN_WIDTH - 1:0] data_ch0_r; //, data_ch1_r;
//assign data_ch0 = data_ch0_r;
//assign data_ch1 = data_ch1_r;
......@@ -125,7 +125,7 @@ module data_producer #(
for (k = 0; k < `N_ADC_CHANNELS/2; k = k + 1)
begin: data_ch1_gen
assign data_ch0[(32 * (k+1) - 1):(32 * k)] = data_ch0_regs[k];
assign data_ch1[(32 * (k+1) - 1):(32 * k)] = data_ch1_regs[k];
assign data_ch1[(32 * k + 31):(32 * k)] = data_ch1_regs[k];
end
endgenerate
/*
......@@ -139,12 +139,12 @@ module data_producer #(
assign adc_eo_data[30] = adc_eorec_f(adc_data[557:540], eo_offset[557:540]);
assign adc_eo_data[31] = adc_eorec_f(adc_data[575:558], eo_offset[575:558]);
*/
/*Fifo input size is 512 (16 * 32 bit). Multiplexing here */
/*Fifo input size is 512 (16 * 32 bit). Multiplexing channels and head/foot here */
integer c;
always @ (posedge clk_100)
if (!ack_en) begin
data_vld_ch0_r <= #TCQ 0;
cnt_pckt_r <= #TCQ {64{1'b0}};
data_vld_ch0_r <= #TCQ 0;
cnt_pckt_ch0_r <= #TCQ 64'h0;
cnt_sample_r <= #TCQ {PKT_SAMPLES_WIDTH {1'b0}};
end
else
......@@ -152,33 +152,61 @@ module data_producer #(
6'h00: begin
if( data_ready_ch0 == 1'b1) // Checks if there is space for 32 ADC samples
data_vld_ch0_r <= #TCQ 1'b1;
//if ( cnt_sample_r == {PKT_SAMPLES_WIDTH {1'b0}}) begin // Header: 4 + 4 bytes Sample Data, Channels 0-3 are sub-coded
//data_ch1_regs[0] <= #TCQ 32'h30003;
//data_ch1_regs[1] <= #TCQ 32'h54310000;
//data_ch1_regs[2] <= #TCQ cnt_ch1_pckt_r[31:0]; // Second position
//data_ch1_regs[3] <= #TCQ cnt_ch1_pckt_r[63:32];
// data_ch1_r[63:00] <= #TCQ {32'h54310000, 32'h30003}; // Type 1: Header
//data_ch1_r[127:64] <= #TCQ cnt_ch1_pckt_r ; // Second position
data_ch0_regs[0] <= #TCQ {8'h54,3'b0, adc_chop, adc_eo_data[0]};
data_ch0_regs[1] <= #TCQ {8'h31,3'b0, adc_chop, adc_eo_data[1]};
data_ch0_regs[2] <= #TCQ {8'hAB,3'b0, adc_chop, adc_eo_data[2]};
data_ch0_regs[3] <= #TCQ {8'hCD,3'b0, adc_chop, adc_eo_data[3]};
data_ch0_regs[4] <= #TCQ {cnt_ch1_pckt_r[7:0],3'b0, adc_chop, adc_eo_data[4]};
for (c = 5; c < `N_ADC_CHANNELS/2; c = c + 1)
data_ch0_regs[c] <= #TCQ {11'h0, adc_chop, adc_eo_data[c]};
if ( cnt_sample_r == {PKT_SAMPLES_WIDTH {1'b0}}) begin // Header: Sample Data, Header data is sub-coded in upper bytes
data_ch0_regs[0] <= #TCQ {8'h00,3'b0, adc_chop, adc_eo_data[0]}; //Magic 0
data_ch0_regs[1] <= #TCQ {8'h01,3'b0, adc_chop, adc_eo_data[1]};
data_ch0_regs[2] <= #TCQ {8'h31,3'b0, adc_chop, adc_eo_data[2]};
data_ch0_regs[3] <= #TCQ {8'h54,3'b0, adc_chop, adc_eo_data[3]};
for (c = 4; c < 8; c = c + 1)
data_ch0_regs[c] <= #TCQ {11'h0, adc_chop, adc_eo_data[c]};
data_ch0_regs[8] <= #TCQ {cnt_pckt_ch0_r[7:0], 3'b0, adc_chop, adc_eo_data[8]};
data_ch0_regs[9] <= #TCQ {cnt_pckt_ch0_r[15:8], 3'b0, adc_chop, adc_eo_data[9]};
data_ch0_regs[10] <= #TCQ {cnt_pckt_ch0_r[23:16],3'b0, adc_chop, adc_eo_data[10]};
data_ch0_regs[11] <= #TCQ {cnt_pckt_ch0_r[31:24],3'b0, adc_chop, adc_eo_data[11]};
data_ch0_regs[12] <= #TCQ {cnt_pckt_ch0_r[39:32],3'b0, adc_chop, adc_eo_data[12]};
data_ch0_regs[13] <= #TCQ {cnt_pckt_ch0_r[47:40],3'b0, adc_chop, adc_eo_data[13]};
data_ch0_regs[14] <= #TCQ {cnt_pckt_ch0_r[53:48],3'b0, adc_chop, adc_eo_data[14]};
data_ch0_regs[15] <= #TCQ {cnt_pckt_ch0_r[63:54],3'b0, adc_chop, adc_eo_data[15]};
end
else begin // Plain samples
for (c = 0; c < `N_ADC_CHANNELS/2; c = c + 1)
data_ch0_regs[c] <= #TCQ {11'h0, adc_chop, adc_eo_data[c]};
end
end
6'h01: begin
data_ch0_regs[0] <= #TCQ {8'h54,3'b0, adc_chop, adc_eo_data[16]};
data_ch0_regs[1] <= #TCQ {8'h31,3'b0, adc_chop, adc_eo_data[17]};
data_ch0_regs[2] <= #TCQ {8'hAB,3'b0, adc_chop, adc_eo_data[18]};
data_ch0_regs[3] <= #TCQ {8'hCD,3'b0, adc_chop, adc_eo_data[19]};
data_ch0_regs[4] <= #TCQ {cnt_ch1_pckt_r[7:0],3'b0, adc_chop, adc_eo_data[20]};
if ( cnt_sample_r == {PKT_SAMPLES_WIDTH {1'b1}}) begin // Footer Sample Data, are sub-coded
cnt_sample_r <= #TCQ {PKT_SAMPLES_WIDTH {1'b0}};
cnt_pckt_ch0_r <= #TCQ cnt_pckt_ch0_r + 1;
data_ch0_regs[0] <= #TCQ {8'hCD,3'b0, adc_chop, adc_eo_data[16]}; //Magic 0
data_ch0_regs[1] <= #TCQ {8'hAB,3'b0, adc_chop, adc_eo_data[17]};
data_ch0_regs[2] <= #TCQ {8'h32,3'b0, adc_chop, adc_eo_data[18]};
data_ch0_regs[3] <= #TCQ {8'h54,3'b0, adc_chop, adc_eo_data[19]};
//data_ch0_regs[4] <= #TCQ {cnt_ch1_pckt_r[7:0],3'b0, adc_chop, adc_eo_data[4]};
for (c = 4; c < 8; c = c + 1)
data_ch0_regs[c] <= #TCQ {11'h0, adc_chop, adc_eo_data[c + `N_ADC_CHANNELS/2]};
data_ch0_regs[8] <= #TCQ {cnt_pckt_ch0_r[7:0], 3'b0, adc_chop, adc_eo_data[24]};
data_ch0_regs[9] <= #TCQ {cnt_pckt_ch0_r[15:8], 3'b0, adc_chop, adc_eo_data[25]};
data_ch0_regs[10] <= #TCQ {cnt_pckt_ch0_r[23:16],3'b0, adc_chop, adc_eo_data[26]};
data_ch0_regs[11] <= #TCQ {cnt_pckt_ch0_r[31:24],3'b0, adc_chop, adc_eo_data[27]};
data_ch0_regs[12] <= #TCQ {cnt_pckt_ch0_r[39:32],3'b0, adc_chop, adc_eo_data[28]};
data_ch0_regs[13] <= #TCQ {cnt_pckt_ch0_r[47:40],3'b0, adc_chop, adc_eo_data[29]};
data_ch0_regs[14] <= #TCQ {cnt_pckt_ch0_r[53:48],3'b0, adc_chop, adc_eo_data[30]};
data_ch0_regs[15] <= #TCQ {cnt_pckt_ch0_r[63:54],3'b0, adc_chop, adc_eo_data[31]};
/*data_ch0_regs[0] <= #TCQ {8'h54,3'b0, adc_chop, adc_eo_data[16]};
data_ch0_regs[1] <= #TCQ {8'h31,3'b0, adc_chop, adc_eo_data[17]};
data_ch0_regs[2] <= #TCQ {8'hAB,3'b0, adc_chop, adc_eo_data[18]};
data_ch0_regs[3] <= #TCQ {8'hCD,3'b0, adc_chop, adc_eo_data[19]};
data_ch0_regs[4] <= #TCQ {cnt_pckt_ch0_r[7:0],3'b0, adc_chop, adc_eo_data[20]};
for (c = 5; c < `N_ADC_CHANNELS/2; c = c + 1)
data_ch0_regs[c] <= #TCQ {11'h0, adc_chop, adc_eo_data[c + `N_ADC_CHANNELS/2]};
if ( cnt_sample_r == {PKT_SAMPLES_WIDTH {1'b1}}) begin // Footer Sample Data, Channels 28-51 are sub-coded
cnt_sample_r <= #TCQ {PKT_SAMPLES_WIDTH {1'b0}};
cnt_pckt_r <= #TCQ cnt_pckt_r + 1;
end
*/
end
else begin // Plain samples
cnt_sample_r <= #TCQ cnt_sample_r + 1;
for (c = 0; c < `N_ADC_CHANNELS/2; c = c + 1)
data_ch0_regs[c] <= #TCQ {11'h0, adc_chop, adc_eo_data[c + `N_ADC_CHANNELS/2]};
end
end
6'h02:
data_vld_ch0_r <= #TCQ 1'b0;
......@@ -301,7 +329,7 @@ module data_producer #(
if (!ack_en) begin
data_vld_ch1_r <= #TCQ 0;
cnt_decim_ch1_r <= #TCQ 0;
cnt_ch1_pckt_r <= #TCQ 0;
cnt_pckt_ch1_r <= #TCQ 0;
end
else
case (clk_100_cnt) // one cycle per sample
......@@ -310,18 +338,18 @@ module data_producer #(
cnt_decim_ch1_r <= #TCQ 0; //{PKT_SAMPLES_WIDTH {1'b0}};
if( data_ready_ch1 == 1'b1) // Checks if there is space for full pckt
data_vld_ch1_r <= #TCQ 1'b1;
cnt_ch1_pckt_r <= #TCQ cnt_ch1_pckt_r + 1;
cnt_pckt_ch1_r <= #TCQ cnt_pckt_ch1_r + 1;
// Fifo in data order is "natural" in xpm_fifo_async
data_ch1_regs[0] <= #TCQ 32'h30003;
data_ch1_regs[1] <= #TCQ 32'h54310000;
data_ch1_regs[2] <= #TCQ cnt_ch1_pckt_r[31:0]; // Second position
data_ch1_regs[3] <= #TCQ cnt_ch1_pckt_r[63:32];
data_ch1_regs[2] <= #TCQ cnt_pckt_ch1_r[31:0]; // Second position
data_ch1_regs[3] <= #TCQ cnt_pckt_ch1_r[63:32];
// data_ch1_r[63:00] <= #TCQ {32'h54310000, 32'h30003}; // Type 1: Header
//data_ch1_r[127:64] <= #TCQ cnt_ch1_pckt_r ; // Second position
//data_ch1_r[127:64] <= #TCQ cnt_pckt_ch1_r ; // Second position
for (c = 4; c < `N_ADC_CHANNELS/2; c = c + 1)
data_ch1_regs[c] <= #TCQ 32'hABCD1235;
//data_ch1_r[511:128] <= #TCQ {12{32'hABCD1235}};
cnt_ch1_foot_r <= #TCQ cnt_ch1_pckt_r ; // save forpcket footer
cnt_ch1_foot_r <= #TCQ cnt_pckt_ch1_r ; // save forpcket footer
end
else
cnt_decim_ch1_r <= #TCQ cnt_decim_ch1_r + 1;
......
......@@ -7,7 +7,7 @@
// Module Name: pci_dma_engine
// Project Name:
// Target Devices: kintex-7
// Tool Versions: Vivado 2018.3
// Tool Versions: Vivado 2019.1
// Description:
//
// Dependencies:
......@@ -15,7 +15,7 @@
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Copyright 2015 - 2017 IPFN-Instituto Superior Tecnico, Portugal
// Copyright 2015 - 2019 IPFN-Instituto Superior Tecnico, Portugal
// Creation Date 2017-11-09
//
// Licensed under the EUPL, Version 1.2 or - as soon they
......@@ -60,10 +60,8 @@ module pci_dma_engine #(
output [7:0] dma_status,
input dma_compl_acq, // No need for MSI irq
input [20:0] dma_size, // in Bytes. MAX size 1 MB = 8k / 4k / 2k TLPs
input [31:0] dma_ha_ch0,
input [31:0] dma_ha_ch0, // dma ch0 host address
input [31:0] dma_ha_ch1,
//From PIO_RX-engine not used
//input req_compl_rx,
//input req_compl_wd_rx,
output reg [7:0] dma_tlp_payload_size, //to TX-DMA-engine - DMA BYTE SIZE in DW
output reg [31:0] host_addr_tx, //to TX-DMA-engine - addr_host_out
......@@ -74,7 +72,7 @@ module pci_dma_engine #(
input dma_tlp_compl_done,
input [31:0] clk_2_cnt, // clk_100 domain
output [63:0] dma_pkt_cnt, // Not used
//output [63:0] dma_pkt_cnt, // Not used
//DMA irq input data channel
input adc_data_clk, //I - clk_100
......@@ -123,8 +121,8 @@ module pci_dma_engine #(
(* mark_debug="yes" *) wire streame_i = control_reg[`STREAME_BIT];
assign dmach0_en_i = control_reg[`DMAE_BIT] ;
reg [2:0] dmae_r;
reg [63:0] dma_pkt_cnt_r;
assign dma_pkt_cnt = dma_pkt_cnt_r;
//reg [63:0] dma_pkt_cnt_r;
//assign dma_pkt_cnt = dma_pkt_cnt_r;
(* mark_debug="yes" *) wire DMAiE = control_reg[`DMAiE_BIT]; //
reg dma_ch_sel_r = 1'b0; // 0: dma_irq, 1:dma_poll
......@@ -169,7 +167,7 @@ module pci_dma_engine #(
dma_tlp_payload_size <= #TCQ 0;
host_addr_tx <= #TCQ 32'b0;
dma_current_buffer <= #TCQ 3'b111; // start at buff = 0
dma_pkt_cnt_r <= #TCQ 0;
//dma_pkt_cnt_r <= #TCQ 0;
dma_ch_sel_r <= 1'b0;
state_rd_wr <= #TCQ DMA_SM_TLP_RST;
......@@ -186,7 +184,7 @@ module pci_dma_engine #(
state_rd_wr <= #TCQ DMA_SM_CH1_1ST_TLP;
end
else if ( req_single_dma_flag && !prog_empty_ch0 && dma_ha_ch0_not_zero) begin // waiting for new user DMA request
dma_pkt_cnt_r <= #TCQ dma_pkt_cnt_r + 1;
//dma_pkt_cnt_r <= #TCQ dma_pkt_cnt_r + 1;
dma_current_buffer <= #TCQ dma_current_buffer + 3'b001; //current buffer change
dma_ch_sel_r <= #TCQ 1'b0;
state_rd_wr <= #TCQ DMA_SM_1ST_TLP;
......@@ -421,7 +419,7 @@ xpm_fifo_async #(
.FIFO_READ_LATENCY(0), // DECIMAL If READ_MODE = "fwft", then the only applicable value is 0.
.FIFO_WRITE_DEPTH(2048), // DECIMAL, FIFO_READ_DEPTH = 16374
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(512), // DECIMAL, Max_Value = (FIFO_WRITE_DEPTH-3) -(READ_MODE_VAL*2)
.PROG_EMPTY_THRESH(4096), // Max_Value = (FIFO_WRITE_DEPTH-3) -(READ_MODE_VAL*2), error in UG953? should be Max=FIFO_READ_DEPTH - ...?
.PROG_FULL_THRESH(2000), // DECIMAL
.RD_DATA_COUNT_WIDTH(15), // DECIMAL log2(FIFO_READ_DEPTH)+1
.READ_DATA_WIDTH(64), // DECIMAL
......@@ -514,14 +512,13 @@ xpm_fifo_async #(
.FIFO_READ_LATENCY(0), // DECIMAL If READ_MODE = "fwft", then the only applicable value is 0.
.FIFO_WRITE_DEPTH(32), // DECIMAL, FIFO_READ_DEPTH = 256
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(8), // DECIMAL, Max_Value = (FIFO_WRITE_DEPTH-3) -(READ_MODE_VAL*2)
.PROG_EMPTY_THRESH(8), // DECIMAL, Max_Value = (FIFO_WRITE_DEPTH-3) -(READ_MODE_VAL*2), TODO CHECK THIS (see other fifo..)
.PROG_FULL_THRESH(24), // DECIMAL
.RD_DATA_COUNT_WIDTH(9), // DECIMAL log2(FIFO_READ_DEPTH)+1
.READ_DATA_WIDTH(64), // DECIMAL
.READ_MODE("fwft"), // String READ_MODE_VAL = 1
.RELATED_CLOCKS(0), // DECIMAL, wr_clk and rd_clk not related
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
//.USE_ADV_FEATURES("0707"), // String
.USE_ADV_FEATURES("0202"), // String
// Setting USE_ADV_FEATURES[1] to 1 enables prog_full flag; Default value of this bit is 1
// Setting USE_ADV_FEATURES[9] to 1 enables prog_empty flag; Default value of this bit is 1
......@@ -530,71 +527,33 @@ xpm_fifo_async #(
.WR_DATA_COUNT_WIDTH(6) // DECIMAL the width should be log2(FIFO_WRITE_DEPTH)+1.
)
dma_fifo_1 (
.almost_empty(), // 1-bit output: Almost Empty : When asserted, this signal indicates that
// only one more read can be performed before the FIFO goes to empty.
.almost_empty(),
.almost_full(), // 1-bit output: Almost Full: When asserted, this signal indicates that
// only one more write can be performed before the FIFO is full.
.data_valid(), // 1-bit output: Read Data Valid: When asserted, this signal indicates
// that valid data is available on the output bus (dout).
//.dbiterr(dbiterr), // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected
// a double-bit error and data in the FIFO core is corrupted.
.dbiterr(), // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected
.dout(fifo_poll_data_out), // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
// when reading the FIFO.
.empty(), // 1-bit output: Empty Flag: When asserted, this signal indicates that the
// FIFO is empty. Read requests are ignored when the FIFO is empty,
// initiating a read while empty is not destructive to the FIFO.
.full(), // 1-bit output: Full Flag: When asserted, this signal indicates that the
// FIFO is full. Write requests are ignored when the FIFO is full,
// initiating a write when the FIFO is full is not destructive to the
// contents of the FIFO.
.overflow(), // 1-bit output: Overflow: This signal indicates that a write request
// (wren) during the prior clock cycle was rejected, because the FIFO is
// full. Overflowing the FIFO is not destructive to the contents of the
// FIFO.
.prog_empty(prog_empty_ch1), // 1-bit output: Programmable Empty: This signal is asserted when the
// number of words in the FIFO is less than or equal to the programmable
// empty threshold value. It is de-asserted when the number of words in
// the FIFO exceeds the programmable empty threshold value.
.prog_full(prog_full_ch1), // 1-bit output: Programmable Full: This signal is asserted when the
// number of words in the FIFO is greater than or equal to the
// programmable full threshold value. It is de-asserted when the number of
// words in the FIFO is less than the programmable full threshold value.
.rd_data_count(), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the
// number of words read from the FIFO.
.rd_rst_busy(), // 1-bit output: Read Reset Busy: Active-High indicator that the FIFO read
// domain is currently in a reset state.
.sbiterr(), // 1-bit output: Single Bit Error: Indicates that the ECC decoder detected
// and fixed a single-bit error.
//.underflow(), // 1-bit output: Underflow: Indicates that the read request (rd_en) during
// the previous clock cycle was rejected because the FIFO is empty. Under
// flowing the FIFO is not destructive to the FIFO.
.underflow(), // 1-bit output: Underflow: Indicates that the read request (rd_en) during
.wr_ack(), // 1-bit output: Write Acknowledge: This signal indicates that a write
// request (wr_en) during the prior clock cycle is succeeded.
.wr_data_count(), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
// the number of words written into the FIFO.
.wr_rst_busy(), // 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
// write domain is currently in a reset state.
.din(data_in_ch1), // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
// writing the FIFO.
.injectdbiterr(1'b0), // 1-bit input: Double Bit Error Injection: Injects a double bit error if
// the ECC feature is used on block RAMs or UltraRAM macros.
.injectsbiterr(1'b0), // 1-bit input: Single Bit Error Injection: Injects a single bit error if
// the ECC feature is used on block RAMs or UltraRAM macros.