i not getting data

linux-software/test/rawdata0_7.gp

+#!/usr/bin/env gnuplot
+#
+#
+clear
+# set term png
+set term png enhanced font '/usr/share/fonts/liberation/LiberationSans-Regular.ttf' 12
+set output 'acqDataRaw.png'
+
+#set xlabel 'Time (s)'
+set xlabel 'Samp'
+#set xlabel 'mSec'
+#set ylabel 'Amp (V)'
+set ylabel 'Amp (LSB)'
+set title 'ATCA v2 DMA data'
+set ytics nomirror
+set y2tics -100, 50
+
+dfile='data.bin'
+
+sampl_freq = 2000000.0
+sampl_per = 0.0000005
+scaleY= 1.0
+#scaleY= 0.0001729
+plot_dec =11
+# 200
+firstl = 1
+endl = 1e5
+
+plot dfile binary format='%64int16' every plot_dec::firstl:0:endl  using ($0*1):(($1)*scaleY) with lines lt 1 lw 1  title 'ch0', \
+     dfile binary format='%64int16' every plot_dec::firstl:0:endl  using ($0*1):(($2)*scaleY) with lines lt 2 lw 1  title 'CntAd' axes x1y2, \
+     dfile binary format='%32int32' every plot_dec::firstl:0:endl  using ($0*1):(($2)*scaleY) with lines lt 3 lw 1  title 'C100', \
+     dfile binary format='%32int32' every plot_dec::firstl:0:endl  using ($0*1):(($9)*scaleY) with lines lt 4 lw 2  title 'Ch8'
+#     dfile binary format='%32int32' every plot_dec::firstl:0:endl  using ($0*1):(($17)*scaleY) with lines lt 1 dt 2  title 'Count'
+     #dfile binary format='%4int16' every plot_dec::firstl:0:endl  using ($0*1):(($3)*scaleY) with lines lt 3 lw 1  title 'Ch6', \
+     #dfile binary format='%4int16' every plot_dec::firstl:0:endl  using ($0*1):(($4)*scaleY) with lines lt 4 lw 1  title 'Ch7'
+
+#set term x11
+set term wxt
+replot
+pause -1 "Hit return to continue"

scripts/project_implement_all.tcl

@@ -9,7 +9,8 @@
 ################################################################################
 set DEBUG_CORE false
 #set DEBUG_CORE true
-set WRITE_MCS true
+
+set WRITE_MCS false
 
 set top_file atca_mimo_v2_adc
 set prog_file atcav2

src/hdl/adc_chan_ddr_sr.v

@@ -127,16 +127,16 @@ module adc_chan_ddr_sr #( IDELAY_VAL = 10 )
     reg [8:1] data_p, data_n;
 
     reg [15:0] count100 = 0;
-    reg [8:0] cnt_reg  = 9'h1;
-    always @ (posedge serial_clock_i or negedge adc_sreg_rst_n ) //begin
+    reg [9:0] cnt_reg  = 10'h001;
+    always @ (posedge serial_clock_i or negedge adc_sreg_rst_n) //begin
         if (!adc_sreg_rst_n)
-            cnt_reg  <=  9'h01; // asyn reset
+            cnt_reg  <=  10'h001; // async reset
            //count100  <=  4'h0;
         else begin
-            //if (cnt_reg == 9'h100)
-                //cnt_reg  <=  9'h001;
+            //if (cnt_reg == 10'h200)
+                //cnt_reg  <=  10'h001;
             //else
-            cnt_reg  <=  {cnt_reg[7:0], 1'b0}; // Left shift reg
+            cnt_reg  <=  {cnt_reg[8:0], 1'b0}; // Left shift reg
 
             count100  <=  count100 + 1'b1;
         end
@@ -144,30 +144,30 @@ module adc_chan_ddr_sr #( IDELAY_VAL = 10 )
 
     always @(negedge serial_clock_i) // "OPPOSITE_EDGE"
         case (cnt_reg)
-            9'h001   : data_p <= 7'd0;
-            9'h002   : data_p[8] <= Qp;
-            9'h004   : data_p[7] <= Qp;
-            9'h008   : data_p[6] <= Qp;
-            9'h010   : data_p[5] <= Qp;
-            9'h020   : data_p[4] <= Qp;
-            9'h040   : data_p[3] <= Qp;
-            9'h080   : data_p[2] <= Qp;
-            9'h100   : data_p[1] <= Qp;
+            10'h001   : data_p <= 7'd0;
+            10'h002   : data_p[8] <= Qp;
+            10'h004   : data_p[7] <= Qp;
+            10'h008   : data_p[6] <= Qp;
+            10'h010   : data_p[5] <= Qp;
+            10'h020   : data_p[4] <= Qp;
+            10'h040   : data_p[3] <= Qp;
+            10'h080   : data_p[2] <= Qp;
+            10'h100   : data_p[1] <= Qp;
             default: ;
         endcase
 
     always @(posedge serial_clock_i)
         case (cnt_reg)
-            //            9'h000   : data_p[8] <= serial_data;
-            9'h001   : data_n <= 7'd0;
-            9'h002   : data_n[8] <= Qn;
-            9'h004   : data_n[7] <= Qn;
-            9'h008   : data_n[6] <= Qn;
-            9'h010   : data_n[5] <= Qn;
-            9'h020   : data_n[4] <= Qn;
-            9'h040   : data_n[3] <= Qn;
-            9'h080   : data_n[2] <= Qn;
-            9'h100   : data_n[1] <= Qn;
+            //            10'h000   : data_p[8] <= serial_data;
+            10'h001   : data_n <= 7'd0;
+            10'h002   : data_n[8] <= Qn;
+            10'h004   : data_n[7] <= Qn;
+            10'h008   : data_n[6] <= Qn;
+            10'h010   : data_n[5] <= Qn;
+            10'h020   : data_n[4] <= Qn;
+            10'h040   : data_n[3] <= Qn;
+            10'h080   : data_n[2] <= Qn;
+            10'h100   : data_n[1] <= Qn;
             default : ;  //data_n <= 8'd0;
         endcase
 

src/hdl/atca_mimo_v2_adc.v

@@ -251,8 +251,7 @@ module atca_mimo_v2_adc # (
     chop_gen chop_gen_inst (
          .clk(adc_word_sync_n_i),
 //         .reset_n(commandREG[STREAME]),  TODO : sync chop...
-         .chop_en(1'b1),
-         //.chop_default(1'b1),
+         .chop_en(1'b0),
          .max_count(32'd2000), //1 KHz chopping
          .change_count(32'd1000),
          .chop_o(adc_chop_i),