Commit 0c2d0947 authored by Bernardo Carvalho's avatar Bernardo Carvalho
Browse files

New Header/Footer, dmaSize: 16512

parent 11b29e20
......@@ -59,12 +59,16 @@ typedef struct _DATA_FLDS {
} DATA_FLDS;
typedef struct _SAMPLE {
volatile uint64_t pckt_header;
DATA_FLDS channel[28];
volatile uint64_t pckt_footer;
// volatile uint64_t pckt_header;
DATA_FLDS channel[32];
// volatile uint64_t pckt_footer;
} SAMPLE;
typedef struct _DMA_PCKT { SAMPLE samp[128]; } DMA_PCKT;
typedef struct _DMA_PCKT {
volatile uint64_t pckt_header[8];
SAMPLE samp[128];
volatile uint64_t pckt_footer[8];
} DMA_PCKT;
char DEVNAME[] = "/dev/atca_v2_0";
char DMADEVNAME[] = "/dev/atca_v2_dma_0";
......@@ -171,15 +175,15 @@ int main(int argc, char **argv) {
/*dmaBuff = (int32_t *)malloc(dmaSize);*/
rc = ioctl(fd, ATCA_PCIE_IOCT_ACQ_ENABLE);
rc = ioctl(fd, ATCA_PCIE_IOCT_STREAM_ENABLE);
rc = ioctl(fd, ATCA_PCIE_IOCT_INT_DISABLE);
/*rc = ioctl(fd, ATCA_PCIE_IOCT_INT_DISABLE);*/
for (i = 0; i < Npackets; i++) {
// printf("wait \n");
/*Pooling Process*/
do {
footer = pdma[buf_num].samp[127].pckt_footer;
footer = pdma[buf_num].pckt_footer[1];
} while (footer <= lastfooter); // wait
header = pdma[buf_num].samp[0].pckt_header;
header = pdma[buf_num].pckt_header[1];
if (header != footer)
printf("pckt: %d, header:%ld, footer:%ld \n", i, header, footer);
lastfooter = footer;
......@@ -188,7 +192,8 @@ int main(int argc, char **argv) {
buf_num++;
if (buf_num == DMA_BUFFS)
buf_num = 0;
/*sleep(1);*/
// usleep(50000);
}
rc = ioctl(fd, ATCA_PCIE_IOCT_STREAM_DISABLE);
usleep(500);
......@@ -206,16 +211,18 @@ int main(int argc, char **argv) {
printf(" \n");
*/
for (i = 0; i < DMA_BUFFS; i++)
printf("%d, ", pdma[i].samp[0].channel[0].buf_num);
printf("%d, ", pdma[i].samp[0].channel[2].buf_num);
printf(" buf_num\n");
for (i = 0; i < DMA_BUFFS; i++)
printf("0x%016lX, ", pdma[i].samp[0].pckt_header);
printf("0x%016lX, ", pdma[i].pckt_header[1]);
printf(" header\n");
/*
*for (i = 0; i < DMA_BUFFS; i++)
* printf("0x%016lX, ", pdma[i].samp[127].pckt_header);
*printf(" 127 header\n");
*/
for (i = 0; i < DMA_BUFFS; i++)
printf("0x%016lX, ", pdma[i].samp[127].pckt_header);
printf(" 127 header\n");
for (i = 0; i < DMA_BUFFS; i++)
printf("0x%016lX, ", pdma[i].samp[127].pckt_footer);
printf("0x%016lX, ", pdma[i].pckt_footer[1]);
printf(" footer\n");
/*
*for (i = 0; i < DMA_BUFFS; i++)
......@@ -230,12 +237,12 @@ int main(int argc, char **argv) {
*/
for (i = 0; i < DMA_BUFFS; i++)
printf("0x%05X, ", pdma[i].samp[0].channel[2].adc_data);
printf(" \n");
printf(" Data \n");
for (i = 0; i < DMA_BUFFS; i++)
printf("0x%05X, ", pdma[i].samp[0].channel[3].adc_data);
printf(" \n");
for (i = 0; i < 32; i++)
printf("0x%05X, ", pdma[0].samp[i].channel[0].adc_data);
printf("0x%05X, ", pdma[0].samp[i].channel[2].adc_data);
printf(" \n");
psamp = (SAMPLE *)map_base;
for (i = 0; i < 32; i++) {
......
......@@ -40,6 +40,7 @@
`timescale 1ns / 1ps
module data_producer #(
parameter DMA_FIFO_DATA_IN_WIDTH = 512, // DMA interface data width
parameter RT_SAMPLES = 128, //
parameter RT_SAMPLES_WIDTH = 7, // 16kB DMA size, 128 samples per packet
//parameter PCKT_COUNT_WIDTH = (RT_SAMPLES_WIDTH + 5), // 32 channel per channel
......@@ -59,11 +60,13 @@ module data_producer #(
reg data_en_r;
assign data_en = data_en_r;
reg [RT_SAMPLES_WIDTH + 63 :0] cnt_data_r;
reg [63 :0] cnt_data_r;
reg [RT_SAMPLES_WIDTH -1 :0] cnt_sample_r;
(* mark_debug="yes" *) wire [7:0] cnt_data_i = cnt_data_r[7:0];
wire [DMA_FIFO_DATA_IN_WIDTH - 1:0] fifo_in_first, fifo_in_second;
reg [DMA_FIFO_DATA_IN_WIDTH - 1:0] fifo_in_first, fifo_in_second;
reg channels_high_r;
/*
//assign fifo_in_first[511:448] = {adc_data[63:32], adc_data[31:0]};
assign fifo_in_first[511:448] = cnt_data_r[RT_SAMPLES_WIDTH + 63:RT_SAMPLES_WIDTH] ; //dma_pkt_cnt; // packet header
......@@ -104,26 +107,63 @@ module data_producer #(
always @ (posedge clk_100) // begin
if (!ack_en) begin
cnt_data_r <= #TCQ 0;
data_en_r <= #TCQ {(RT_SAMPLES_WIDTH + 64){1'b0}};
channels_high_r <= #TCQ 1'b1;
data_en_r <= #TCQ 0;
cnt_data_r <= #TCQ {64{1'b0}};
cnt_sample_r <= #TCQ {RT_SAMPLES_WIDTH {1'b0}};
channels_high_r <= #TCQ 1'b0;
end
else
case (clk_100_cnt) // one cycle per sample
6'h0: begin
data_en_r <= #TCQ 1'b1;
channels_high_r <= #TCQ 1'b0;
// Header: 64 bytes
if ( cnt_sample_r == {RT_SAMPLES_WIDTH {1'b0}}) begin
fifo_in_first[511:448] <= 64'h01;
fifo_in_first[447:384] <= cnt_data_r[63:0] ;
fifo_in_first[383:0] <= 0;
data_en_r <= #TCQ 1'b1;
end
end
6'h1: begin
data_en_r <= #TCQ 1'b1;
fifo_in_first[511:448] <= cnt_data_r[63:0] ;
fifo_in_first[447:384] <= {adc_data[15:8], dma_status[5:0], adc_data[71:54], adc_data[7:0], dma_status[5:0], adc_data[53:36]}; // channels 2,3 and first two bytes of channel 0
fifo_in_first[383:320] <= {{8{adc_data[17]}}, dma_status[5:0], adc_data[107:90], {6{adc_data[17]}}, adc_data[17:16], dma_status[5:0], adc_data[89:72]}; // channels 4,5 and last two bytes of channel 0 , byte extended
fifo_in_first[319:256] <= {adc_data[33:26], dma_status[5:0], adc_data[143:126],
adc_data[25:18], dma_status[5:0], adc_data[125:108]}; // channels 6,7 and first two bytes of channel 1
fifo_in_first[255:192] <= {{8{adc_data[35]}}, dma_status[5:0], adc_data[179:162],
{6{adc_data[35]}}, adc_data[35:34], dma_status[5:0], adc_data[161:144]}; // channels 8,9 and last two bytes of channel 1 , byte extended
fifo_in_first[191:0] <= 0;
end
6'h2: begin
channels_high_r <= #TCQ 1'b1;
fifo_in_second[511:64] <= 0;
end
//6'h1: adc_data_r <= {cnt_data_r, 1'b1, 4'h1, cnt_data_r, 1'b0, 4'h1};
//6'hF:
//adc_data_r <= {cnt_data_r, 1'b1, 4'hF, cnt_data_r, 1'b0, 4'hF};
//6'h10: begin
6'h2: begin
6'h3: begin
channels_high_r <= #TCQ 1'b0;
if ( cnt_sample_r == {RT_SAMPLES_WIDTH {1'b1}}) begin
cnt_sample_r <= #TCQ {RT_SAMPLES_WIDTH {1'b0}};
cnt_data_r <= #TCQ cnt_data_r + 1;
//Footer
fifo_in_first[511:448] <= 64'h02; // TODO set format
fifo_in_first[447:384] <= cnt_data_r[63:0] ;
fifo_in_first[383:0] <= 0;
data_en_r <= #TCQ 1'b1;
end
else begin
cnt_sample_r <= cnt_sample_r + 1;
data_en_r <= #TCQ 1'b0;
end
end
6'h4: begin
data_en_r <= #TCQ 1'b0;
cnt_data_r <= #TCQ cnt_data_r + 1;
// channels_high_r <= #TCQ 1'b0;
end
default: ;
endcase
......
......@@ -378,15 +378,15 @@ module pci_dma_engine #(
.rst(dma_fifo_rst),
.wr_clk(adc_data_clk),
.wr_en(adc_data_en),//
.din(fifo_data_in), // adc_data 512-b = 64 Bytes
.din(fifo_data_in), // adc_data 512b = 64 Bytes
.rd_clk(pcie_user_clk),
.rd_en(fifo_rd_i),
.dout(fifo_data_out), //64b
.empty(fifo_empty_i), //
.dout(fifo_data_out), // PCIe 64b
.empty(fifo_empty_i),
.full(fifo_full_i),
.prog_full_thresh(11'h100), // Max= (h800-1) = 2047 (512b), 256 * 64 = 16kB input wire [10 : 0]
.prog_full(fifo_prog_full_i),
.prog_empty_thresh(14'h0800), // Max= (h4000-1) = 16383 (64b), 2048 * 8 = 16kB input wire [13 : 0] prog_empty_thresh 512 * 8 = 4kB
.prog_empty_thresh(14'h0808), // Max= (h4000-1) = 16383 (64b), 2048 * 8 = 16kB input wire [13 : 0] prog_empty_thresh 512 * 8 = 4kB
.prog_empty(fifo_prog_empty_i)
//.wr_rst_busy(), // O safety circuit
//.rd_rst_busy() // O
......
......@@ -87,7 +87,7 @@
`define MOD_DMA_FULL_RST_CAPAB 1'b0
`define MOD_DMA_INTERRUPT_ID 32'h00000000
`define MOD_DMA_MAX_BYTES 32'h00004000 // 16kB
`define MOD_DMA_MAX_BYTES 32'h00004080 // 16kB + 128 = 16512
`define MOD_DMA_TLP_PAYLOAD 32'h00000020 // 32 DW 128 B
`define MOD_CNTRL_FULL_RST_BIT 31
......
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