Commit 813f81c2 authored by Andreas Marek's avatar Andreas Marek

Merge branch 'master_pre_stage' into 'master'

Master pre stage

See merge request !45
parents 5e8600ec 5e2d39a6
......@@ -2,6 +2,7 @@ Changelog for next release
- not yet decided
- fix determination whether a _ is needed to link Fortran to C
- Bugfix: add missing test_scalapack_template.F90 to EXTRA_DIST list
Changelog for ELPA 2020.05.001
......
......@@ -757,6 +757,7 @@ EXTRA_DIST = \
test/shared/test_check_correctness_template.F90 \
test/shared/test_prepare_matrix_template.F90 \
test/shared/test_analytic_template.F90 \
test/shared/test_scalapack_template.F90 \
test_project_1stage/Makefile.am \
test_project_1stage/autogen.sh \
test_project_1stage/configure.ac \
......
......@@ -570,7 +570,7 @@ if test x"${have_mkl}" = x"yes" ; then
else
dnl first check blas
AC_SEARCH_LIBS([dgemm],[openblas satlas blas],[have_blas=yes],[have_blas=no])
AC_SEARCH_LIBS([dgemm],[flexiblas openblas satlas blas],[have_blas=yes],[have_blas=no])
AC_MSG_CHECKING([whether we can link a program with a blas lib])
AC_MSG_RESULT([${have_blas}])
......
......@@ -184,7 +184,7 @@
#ifdef DOUBLE_PRECISION_REAL
#define offset 2
#define __SIMD_DATATYPE __vector double
#define __SIMD_LOAD (__vector double) vec_ld
#define _SIMD_LOAD (__vector double) vec_ld
#endif
#ifdef SINGLE_PRECISION_REAL
......@@ -197,9 +197,10 @@
#define _SIMD_STORE vec_st
#define _SIMD_ADD vec_add
#define _SIMD_MUL vec_mul
#define _SIMD_SUB vec_sub
#define _SIMD_SET1 vec_splats
#endif /* VEC_SET == SPARC64_SSE */
#endif /* VEC_SET == VSX_SSE */
#if VEC_SET == NEON_ARCH64_128
#define __ELPA_USE_FMA__
......@@ -1629,7 +1630,7 @@ void CONCAT_7ARGS(PREFIX,_hh_trafo_real_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA
#undef ROW_LENGTH
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == NEON_ARCH64_128
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == VSX_SSE || VEC_SET == NEON_ARCH64_128
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 6
#define STEP_SIZE 6
......@@ -1680,7 +1681,7 @@ void CONCAT_7ARGS(PREFIX,_hh_trafo_real_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA
#undef ROW_LENGTH
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == NEON_ARCH64_128
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == VSX_SSE || VEC_SET == NEON_ARCH64_128
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 4
#endif
......@@ -1715,7 +1716,7 @@ void CONCAT_7ARGS(PREFIX,_hh_trafo_real_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA
}
#undef ROW_LENGTH
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == NEON_ARCH64_128
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == VSX_SSE || VEC_SET == NEON_ARCH64_128
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 2
#endif
......@@ -1772,7 +1773,7 @@ void CONCAT_7ARGS(PREFIX,_hh_trafo_real_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA
#ifdef BLOCK6
#undef ROW_LENGTH
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == NEON_ARCH64_128
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == VSX_SSE || VEC_SET == NEON_ARCH64_128
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 4
#define STEP_SIZE 4
......@@ -1822,7 +1823,7 @@ void CONCAT_7ARGS(PREFIX,_hh_trafo_real_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA
}
#undef ROW_LENGTH
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == NEON_ARCH64_128
#if VEC_SET == SSE_128 || VEC_SET == SPARC64_SSE || VEC_SET == VSX_SSE || VEC_SET == NEON_ARCH64_128
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 2
#endif
......
......@@ -51,7 +51,7 @@
#define BLOCK4 1
#define SIMD_SET VSX_SSE
#include "../../general/precision_macros.h"
#include "real_vsx_4hv_template.c"
#include "real_128bit_256bit_512bit_BLOCK_template.c"
#undef BLOCK4
#undef SIMD_SET
#undef REALCASE
......
......@@ -51,9 +51,8 @@
#define BLOCK4 1
#define SIMD_SET VSX_SSE
#include "../../general/precision_macros.h"
#include "real_vsx_4hv_template.c"
#include "real_128bit_256bit_512bit_BLOCK_template.c"
#undef BLOCK4
#undef SIMD_SET
#undef REALCASE
#undef SINGLE_PRECISION
......@@ -51,7 +51,7 @@
#define BLOCK6 1
#define SIMD_SET VSX_SSE
#include "../../general/precision_macros.h"
#include "real_vsx_6hv_template.c"
#include "real_128bit_256bit_512bit_BLOCK_template.c"
#undef BLOCK6
#undef SIMD_SET
#undef REALCASE
......
......@@ -51,7 +51,7 @@
#define BLOCK6 1
#define VEC_SET VSX_SSE
#include "../../general/precision_macros.h"
#include "real_vsx_6hv_template.c"
#include "real_128bit_256bit_512bit_BLOCK_template.c"
#undef VEC_SET
#undef BLOCK6
#undef REALCASE
......
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