real_128bit_BLOCK_template.c 475 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
//    This file is part of ELPA.
//
//    The ELPA library was originally created by the ELPA consortium,
//    consisting of the following organizations:
//
//    - Max Planck Computing and Data Facility (MPCDF), formerly known as
//      Rechenzentrum Garching der Max-Planck-Gesellschaft (RZG),
//    - Bergische Universität Wuppertal, Lehrstuhl für angewandte
//      Informatik,
//    - Technische Universität München, Lehrstuhl für Informatik mit
//      Schwerpunkt Wissenschaftliches Rechnen ,
//    - Fritz-Haber-Institut, Berlin, Abt. Theorie,
//    - Max-Plack-Institut für Mathematik in den Naturwissenschaften,
//      Leipzig, Abt. Komplexe Strukutren in Biologie und Kognition,
//      and
//    - IBM Deutschland GmbH
//
18
//
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
//    This particular source code file contains additions, changes and
//    enhancements authored by Intel Corporation which is not part of
//    the ELPA consortium.
//
//    More information can be found here:
//    http://elpa.mpcdf.mpg.de/
//
//    ELPA is free software: you can redistribute it and/or modify
//    it under the terms of the version 3 of the license of the
//    GNU Lesser General Public License as published by the Free
//    Software Foundation.
//
//    ELPA is distributed in the hope that it will be useful,
//    but WITHOUT ANY WARRANTY; without even the implied warranty of
//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
//    GNU Lesser General Public License for more details.
//
//    You should have received a copy of the GNU Lesser General Public License
//    along with ELPA. If not, see <http://www.gnu.org/licenses/>
//
//    ELPA reflects a substantial effort on the part of the original
//    ELPA consortium, and we ask you to respect the spirit of the
//    license that we chose: i.e., please contribute any changes you
//    may have back to the original ELPA library distribution, and keep
//    any derivatives of ELPA under the same license that we chose for
//    the original distribution, the GNU Lesser General Public License.
//
// Author: Andreas Marek, MPCDF, based on the double precision case of A. Heinecke
//
#include "config-f90.h"

50
51
52
53
54
55
#define CONCAT_8ARGS(a, b, c, d, e, f, g, h) CONCAT2_8ARGS(a, b, c, d, e, f, g, h)
#define CONCAT2_8ARGS(a, b, c, d, e, f, g, h) a ## b ## c ## d ## e ## f ## g ## h

#define CONCAT_7ARGS(a, b, c, d, e, f, g) CONCAT2_7ARGS(a, b, c, d, e, f, g)
#define CONCAT2_7ARGS(a, b, c, d, e, f, g) a ## b ## c ## d ## e ## f ## g

56
57
58
59
60
61
62
63
64
65
66
67
#define CONCAT_6ARGS(a, b, c, d, e, f) CONCAT2_6ARGS(a, b, c, d, e, f)
#define CONCAT2_6ARGS(a, b, c, d, e, f) a ## b ## c ## d ## e ## f

#define CONCAT_5ARGS(a, b, c, d, e) CONCAT2_5ARGS(a, b, c, d, e)
#define CONCAT2_5ARGS(a, b, c, d, e) a ## b ## c ## d ## e

#define CONCAT_4ARGS(a, b, c, d) CONCAT2_4ARGS(a, b, c, d)
#define CONCAT2_4ARGS(a, b, c, d) a ## b ## c ## d

#define CONCAT_3ARGS(a, b, c) CONCAT2_3ARGS(a, b, c)
#define CONCAT2_3ARGS(a, b, c) a ## b ## c

68
#if VEC_SET == 128 || VEC_SET == 256
69
70
#include <x86intrin.h>
#endif
71
#if VEC_SET == 1281
72
73
74
75
76
77
#include <fjmfunc.h>
#include <emmintrin.h>
#endif
#include <stdio.h>
#include <stdlib.h>

78
79
80
81
82
#ifdef BLOCK6
#define PREFIX hexa
#define BLOCK 6
#endif

83
84
85
86
87
88
89
90
91
92
#ifdef BLOCK4
#define PREFIX quad
#define BLOCK 4
#endif

#ifdef BLOCK2
#define PREFIX double
#define BLOCK 2
#endif

93
#if VEC_SET == 128
94
95
96
#define SIMD_SET SSE
#endif

97
#if VEC_SET == 1281
98
99
#define SIMD_SET SPARC64
#endif
100
101
102
103
104

#if VEC_SET == 256
#define SIMD_SET AVX_AVX2
#endif

105
106
#define __forceinline __attribute__((always_inline)) static

107
#if VEC_SET == 128 || VEC_SET == 1281
108
109
#ifdef DOUBLE_PRECISION_REAL
#define offset 2
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
#define __SIMD_DATATYPE __m128d
#define _SIMD_LOAD _mm_load_pd
#define _SIMD_STORE _mm_store_pd
#define _SIMD_ADD _mm_add_pd
#define _SIMD_MUL _mm_mul_pd
#define _SIMD_SUB _mm_sub_pd
#define _SIMD_XOR _mm_xor_pd
#endif
#ifdef SINGLE_PRECISION_REAL
#define offset 4
#define __SIMD_DATATYPE __m128
#define _SIMD_LOAD _mm_load_ps
#define _SIMD_STORE _mm_store_ps
#define _SIMD_ADD _mm_add_ps
#define _SIMD_MUL _mm_mul_ps
#define _SIMD_SUB _mm_sub_ps
#define _SIMD_XOR _mm_xor_ps
#endif
#endif /* VEC_SET == 128 || VEC_SET == 1281 */
129

130
131
132
133
134
135
136
137
#if VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define offset 4
#define __SIMD_DATATYPE __m256d
#define _SIMD_LOAD _mm256_load_pd
#define _SIMD_STORE _mm256_store_pd
#define _SIMD_ADD _mm256_add_pd
#define _SIMD_MUL _mm256_mul_pd
138
#define _SIMD_SUB _mm256_sub_pd
139
140
141
142
143
144
#define _SIMD_XOR _mm256_xor_pd
#define _SIMD_BROADCAST _mm256_broadcast_sd
#ifdef HAVE_AVX2
#ifdef __FMA4__
#define __ELPA_USE_FMA__
#define _mm256_FMA_pd(a,b,c) _mm256_macc_pd(a,b,c)
145
146
147
148
#define _mm256_NFMA_pd(a,b,c) _mm256_nmacc_pd(a,b,c)
#error "This should be prop _mm256_msub_pd instead of _mm256_msub"
#define _mm256_FMSUB_pd(a,b,c) _mm256_msub(a,b,c)
#endif /* __FMA4__ */
149
150
151
#ifdef __AVX2__
#define __ELPA_USE_FMA__
#define _mm256_FMA_pd(a,b,c) _mm256_fmadd_pd(a,b,c)
152
153
154
155
#define _mm256_NFMA_pd(a,b,c) _mm256_fnmadd_pd(a,b,c)
#define _mm256_FMSUB_pd(a,b,c) _mm256_fmsub_pd(a,b,c)
#endif /* __AVX2__ */
#ifdef __ELPA_USE_FMA__
156
#define _SIMD_FMA _mm256_FMA_pd
157
158
#define _SIMD_NFMA _mm256_NFMA_pd
#define _SIMD_FMSUB _mm256_FMSUB_pd
159
160
161
162
163
164
165
166
167
168
169
#endif
#endif /* HAVE_AVX2 */
#endif /* DOUBLE_PRECISION_REAL */

#ifdef SINGLE_PRECISION_REAL
#define offset 8
#define __SIMD_DATATYPE __m256
#define _SIMD_LOAD _mm256_load_ps
#define _SIMD_STORE _mm256_store_ps
#define _SIMD_ADD _mm256_add_ps
#define _SIMD_MUL _mm256_mul_ps
170
#define _SIMD_SUB _mm256_sub_ps
171
172
173
174
175
176
#define _SIMD_XOR _mm256_xor_ps
#define _SIMD_BROADCAST _mm256_broadcast_ss
#ifdef HAVE_AVX2
#ifdef __FMA4__
#define __ELPA_USE_FMA__
#define _mm256_FMA_ps(a,b,c) _mm256_macc_ps(a,b,c)
177
178
179
180
#define _mm256_NFMA_ps(a,b,c) _mm256_nmacc_ps(a,b,c)
#error "This should be prop _mm256_msub_ps instead of _mm256_msub"
#define _mm256_FMSUB_ps(a,b,c) _mm256_msub(a,b,c)
#endif /* __FMA4__ */
181
182
183
#ifdef __AVX2__
#define __ELPA_USE_FMA__
#define _mm256_FMA_ps(a,b,c) _mm256_fmadd_ps(a,b,c)
184
185
186
187
#define _mm256_NFMA_ps(a,b,c) _mm256_fnmadd_ps(a,b,c)
#define _mm256_FMSUB_ps(a,b,c) _mm256_fmsub_ps(a,b,c)
#endif /* __AVX2__ */
#ifdef __ELPA_USE_FMA__
188
#define _SIMD_FMA _mm256_FMA_ps
189
190
#define _SIMD_NFMA _mm256_NFMA_ps
#define _SIMD_FMSUB _mm256_FMSUB_ps
191
192
193
194
195
196
#endif
#endif /* HAVE_AVX2 */
#endif /* SINGLE_PRECISION_REAL */
#endif /* VEC_SET == 256 */

#ifdef DOUBLE_PRECISION_REAL
197
#define WORD_LENGTH double
198
199
#define DATA_TYPE double
#define DATA_TYPE_PTR double*
200
201
202
203
204
205
206
207
208
209
#endif
#ifdef SINGLE_PRECISION_REAL
#define WORD_LENGTH single
#define DATA_TYPE float
#define DATA_TYPE_PTR float*
#endif


#ifdef DOUBLE_PRECISION_REAL

210
211
212
213
214
215
216
217
218
219
220
221
222
223

#define _SSE_SET _mm_set_pd
#define _SSE_SET1 _mm_set1_pd
#define _SSE_SET _mm_set_pd
#endif

#ifdef SINGLE_PRECISION_REAL

#define _SSE_SET _mm_set_ps
#define _SSE_SET1 _mm_set1_ps
#define _SSE_SET _mm_set_ps

#endif

224
#if VEC_SET == 128
225
226
227
#undef __AVX__
#endif

228
229

#if VEC_SET == 128 || VEC_SET == 1281
230
231
//Forward declaration
#ifdef DOUBLE_PRECISION_REAL
232
233
#undef ROW_LENGTH
#define ROW_LENGTH 2
234
#endif
235
236
237
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 4
238
#endif
239
#endif /* VEC_SET == 128 || VEC_SET == 1281 */
240

241
242
243
244
245
246
247
248
249
250
#if VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 4
#endif
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 8
#endif
#endif /* VEC_SET == 256 */
251
__forceinline void CONCAT_8ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA_TYPE_PTR q, DATA_TYPE_PTR hh, int nb, int ldq, int ldh, 
252
#ifdef BLOCK2
253
	DATA_TYPE s);
254
255
#endif
#ifdef BLOCK4
256
	DATA_TYPE s_1_2, DATA_TYPE s_1_3, DATA_TYPE s_2_3, DATA_TYPE s_1_4, DATA_TYPE s_2_4, DATA_TYPE s_3_4);
257
#endif
258
259
#ifdef BLOCK6
	DATA_TYPE_PTR scalarprods);
260
#endif
261

262
#if VEC_SET == 128 || VEC_SET == 1281
263
264
265
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 4
266
#endif
267
268
269
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 8
270
#endif
271
272
273
274
275
276
277
278
279
280
281
282
#endif /* VEC_SET == 128 || VEC_SET == 1281 */

#if VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 8
#endif
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 16
#endif
#endif /* VEC_SET == 256 */
283
__forceinline void CONCAT_8ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA_TYPE_PTR q, DATA_TYPE_PTR hh, int nb, int ldq, int ldh, 
284
#ifdef BLOCK2
285
	DATA_TYPE s);
286
287
#endif
#ifdef BLOCK4
288
	DATA_TYPE s_1_2, DATA_TYPE s_1_3, DATA_TYPE s_2_3, DATA_TYPE s_1_4, DATA_TYPE s_2_4, DATA_TYPE s_3_4);
289
#endif
290
291
#ifdef BLOCK6
	DATA_TYPE_PTR scalarprods);
292
#endif
293

294
#if VEC_SET == 128 || VEC_SET == 1281 
295
296
297
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 6
298
299
#endif
#ifdef SINGLE_PRECISION_REAL
300
301
#undef ROW_LENGTH
#define ROW_LENGTH 12
302
#endif
303
304
305
306
307
308
309
310
311
312
313
314
315
#endif /* VEC_SET == 128 || VEC_SET == 1281  */

#if VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 12
#endif
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 24
#endif
#endif /* VEC_SET == 256 */

316
__forceinline void CONCAT_8ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA_TYPE_PTR q, DATA_TYPE_PTR hh, int nb, int ldq, int ldh,
317
#ifdef BLOCK2
318
	DATA_TYPE s);
319
320
#endif
#ifdef BLOCK4
321
	DATA_TYPE s_1_2, DATA_TYPE s_1_3, DATA_TYPE s_2_3, DATA_TYPE s_1_4, DATA_TYPE s_2_4, DATA_TYPE s_3_4);
322
#endif
323
324
#ifdef BLOCK6
	DATA_TYPE_PTR scalarprods);
325
#endif
326

327
#if VEC_SET == 128 || VEC_SET == 1281 
328
329
330
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 8
331
#endif
332
333
334
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 16
335
#endif
336
337
338
339
340
341
342
343
344
345
346
347
348
#endif /* VEC_SET == 128 || VEC_SET == 1281  */

#if VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 16
#endif
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 32
#endif
#endif /* VEC_SET == 256 */

349
__forceinline void CONCAT_8ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA_TYPE_PTR q, DATA_TYPE_PTR hh, int nb, int ldq, int ldh, 
350
#ifdef BLOCK2
351
	DATA_TYPE s);
352
353
#endif
#ifdef BLOCK4
354
	DATA_TYPE s_1_2, DATA_TYPE s_1_3, DATA_TYPE s_2_3, DATA_TYPE s_1_4, DATA_TYPE s_2_4, DATA_TYPE s_3_4);
355
#endif
356
357
#ifdef BLOCK6
	DATA_TYPE_PTR scalarprods);
358
#endif
359

360
#if  VEC_SET == 128 || VEC_SET == 1281
361
362
363
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 10
364
#endif
365
366
367
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 20
368
#endif
369
370
371
372
373
374
375
376
377
378
379
380
381
382
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */

#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 20
#endif
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 40
#endif
#endif /*  VEC_SET == 256 */


383
__forceinline void CONCAT_8ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA_TYPE_PTR q, DATA_TYPE_PTR hh, int nb, int ldq, int ldh, 
384
#ifdef BLOCK2
385
	DATA_TYPE s);
386
387
#endif
#ifdef BLOCK4
388
389
390
391
	DATA_TYPE s_1_2, DATA_TYPE s_1_3, DATA_TYPE s_2_3, DATA_TYPE s_1_4, DATA_TYPE s_2_4, DATA_TYPE s_3_4);
#endif
#ifdef BLOCK6
	DATA_TYPE_PTR scalarprods);
392
393
#endif

394
#if  VEC_SET == 128 || VEC_SET == 1281
395
#ifdef DOUBLE_PRECISION_REAL
396
397
#undef ROW_LENGTH
#define ROW_LENGTH 12
398
399
#endif
#ifdef SINGLE_PRECISION_REAL
400
401
402
#undef ROW_LENGTH
#define ROW_LENGTH 24
#endif
403
404
405
406
407
408
409
410
411
412
413
414
#endif /* VEC_SET == 128 || VEC_SET == 1281 */

#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 24
#endif
#ifdef SINGLE_PRECISION_REAL
#undef ROW_LENGTH
#define ROW_LENGTH 48
#endif
#endif /*  VEC_SET == 256 */
415
416
417
418

__forceinline void CONCAT_8ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA_TYPE_PTR q, DATA_TYPE_PTR hh, int nb, int ldq, int ldh,
#ifdef BLOCK2
	DATA_TYPE s);
419
#endif
420
421
422
423
424
425
426
427
#ifdef BLOCK4
	DATA_TYPE s_1_2, DATA_TYPE s_1_3, DATA_TYPE s_2_3, DATA_TYPE s_1_4, DATA_TYPE s_2_4, DATA_TYPE s_3_4);
#endif
#ifdef BLOCK6
	DATA_TYPE_PTR scalarprods);
#endif

void CONCAT_7ARGS(PREFIX,_hh_trafo_real_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA_TYPE_PTR q, DATA_TYPE_PTR hh, int* pnb, int* pnq, int* pldq, int* pldh);
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483

/*
!f>#ifdef HAVE_SSE_INTRINSICS
!f> interface
!f>   subroutine double_hh_trafo_real_SSE_2hv_double(q, hh, pnb, pnq, pldq, pldh) &
!f>                                bind(C, name="double_hh_trafo_real_SSE_2hv_double")
!f>        use, intrinsic :: iso_c_binding
!f>        integer(kind=c_int)        :: pnb, pnq, pldq, pldh
!f>        type(c_ptr), value        :: q
!f>        real(kind=c_double)        :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/
/*
!f>#ifdef HAVE_SSE_INTRINSICS
!f> interface
!f>   subroutine double_hh_trafo_real_SSE_2hv_single(q, hh, pnb, pnq, pldq, pldh) &
!f>              bind(C, name="double_hh_trafo_real_SSE_2hv_single")
!f>     use, intrinsic :: iso_c_binding
!f>     integer(kind=c_int) :: pnb, pnq, pldq, pldh
!f>     type(c_ptr), value  :: q
!f>     real(kind=c_float)  :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/

/*
!f>#ifdef HAVE_SPARC64_SSE
!f> interface
!f>   subroutine double_hh_trafo_real_SPARC64_2hv_double(q, hh, pnb, pnq, pldq, pldh) &
!f>              bind(C, name="double_hh_trafo_real_SPARC64_2hv_double")
!f>     use, intrinsic :: iso_c_binding
!f>     integer(kind=c_int) :: pnb, pnq, pldq, pldh
!f>     type(c_ptr), value  :: q
!f>     real(kind=c_double) :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/

/*
!f>#ifdef HAVE_SPARC64_SSE
!f> interface
!f>   subroutine double_hh_trafo_real_SPARC64_2hv_single(q, hh, pnb, pnq, pldq, pldh) &
!f>              bind(C, name="double_hh_trafo_real_SPARC64_2hv_single")
!f>     use, intrinsic :: iso_c_binding
!f>     integer(kind=c_int) :: pnb, pnq, pldq, pldh
!f>     type(c_ptr), value  :: q
!f>     real(kind=c_float)  :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/

484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
/*
!f>#if defined(HAVE_AVX) || defined(HAVE_AVX2)
!f> interface
!f>   subroutine double_hh_trafo_real_AVX_AVX2_2hv_double(q, hh, pnb, pnq, pldq, pldh) &
!f>                                bind(C, name="double_hh_trafo_real_AVX_AVX2_2hv_double")
!f>        use, intrinsic :: iso_c_binding
!f>        integer(kind=c_int)        :: pnb, pnq, pldq, pldh
!f>        type(c_ptr), value        :: q
!f>        real(kind=c_double)        :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/

/*
!f>#if defined(HAVE_AVX) || defined(HAVE_AVX2)
!f> interface
!f>   subroutine double_hh_trafo_real_AVX_AVX2_2hv_single(q, hh, pnb, pnq, pldq, pldh) &
!f>                                bind(C, name="double_hh_trafo_real_AVX_AVX2_2hv_single")
!f>        use, intrinsic :: iso_c_binding
!f>        integer(kind=c_int)       :: pnb, pnq, pldq, pldh
!f>        type(c_ptr), value        :: q
!f>        real(kind=c_float)        :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/

512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
/*
!f>#ifdef HAVE_SSE_INTRINSICS
!f> interface
!f>   subroutine quad_hh_trafo_real_SSE_4hv_double(q, hh, pnb, pnq, pldq, pldh) &
!f>                                bind(C, name="quad_hh_trafo_real_SSE_4hv_double")
!f>        use, intrinsic :: iso_c_binding
!f>        integer(kind=c_int)        :: pnb, pnq, pldq, pldh
!f>        type(c_ptr), value        :: q
!f>        real(kind=c_double)        :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/
/*
!f>#ifdef HAVE_SSE_INTRINSICS
!f> interface
!f>   subroutine quad_hh_trafo_real_SSE_4hv_single(q, hh, pnb, pnq, pldq, pldh) &
!f>              bind(C, name="quad_hh_trafo_real_SSE_4hv_single")
!f>     use, intrinsic :: iso_c_binding
!f>     integer(kind=c_int) :: pnb, pnq, pldq, pldh
!f>     type(c_ptr), value  :: q
!f>     real(kind=c_float)  :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/

/*
!f>#ifdef HAVE_SPARC64_SSE
!f> interface
!f>   subroutine quad_hh_trafo_real_SPARC64_4hv_double(q, hh, pnb, pnq, pldq, pldh) &
!f>              bind(C, name="quad_hh_trafo_real_SPARC64_4hv_double")
!f>     use, intrinsic :: iso_c_binding
!f>     integer(kind=c_int) :: pnb, pnq, pldq, pldh
!f>     type(c_ptr), value  :: q
!f>     real(kind=c_double) :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/

/*
!f>#ifdef HAVE_SPARC64_SSE
!f> interface
!f>   subroutine quad_hh_trafo_real_SPARC64_4hv_single(q, hh, pnb, pnq, pldq, pldh) &
!f>              bind(C, name="quad_hh_trafo_real_SPARC64_4hv_single")
!f>     use, intrinsic :: iso_c_binding
!f>     integer(kind=c_int) :: pnb, pnq, pldq, pldh
!f>     type(c_ptr), value  :: q
!f>     real(kind=c_float)  :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593

/*
!f>#if defined(HAVE_AVX) || defined(HAVE_AVX2)
!f> interface
!f>   subroutine quad_hh_trafo_real_AVX_AVX2_4hv_double(q, hh, pnb, pnq, pldq, pldh) &
!f>                                bind(C, name="quad_hh_trafo_real_AVX_AVX2_4hv_double")
!f>        use, intrinsic :: iso_c_binding
!f>        integer(kind=c_int)        :: pnb, pnq, pldq, pldh
!f>        type(c_ptr), value        :: q
!f>        real(kind=c_double)        :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/
/*
!f>#if defined(HAVE_AVX) || defined(HAVE_AVX2)
!f> interface
!f>   subroutine quad_hh_trafo_real_AVX_AVX2_4hv_single(q, hh, pnb, pnq, pldq, pldh) &
!f>              bind(C, name="quad_hh_trafo_real_AVX_AVX2_4hv_single")
!f>     use, intrinsic :: iso_c_binding
!f>     integer(kind=c_int) :: pnb, pnq, pldq, pldh
!f>     type(c_ptr), value  :: q
!f>     real(kind=c_float)  :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/

594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
/*
!f>#ifdef HAVE_SSE_INTRINSICS
!f> interface
!f>   subroutine hexa_hh_trafo_real_sse_6hv_double(q, hh, pnb, pnq, pldq, pldh) &
!f>                                bind(C, name="hexa_hh_trafo_real_SSE_6hv_double")
!f>        use, intrinsic :: iso_c_binding
!f>        integer(kind=c_int)        :: pnb, pnq, pldq, pldh
!f>        type(c_ptr), value        :: q
!f>        real(kind=c_double)        :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/
/*
!f>#ifdef HAVE_SPARC64_SSE
!f> interface
!f>   subroutine hexa_hh_trafo_real_sparc64_6hv_double(q, hh, pnb, pnq, pldq, pldh) &
!f>                                bind(C, name="hexa_hh_trafo_real_SPARC64_6hv_double")
!f>        use, intrinsic :: iso_c_binding
!f>        integer(kind=c_int)        :: pnb, pnq, pldq, pldh
!f>        type(c_ptr), value        :: q
!f>        real(kind=c_double)        :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/
/*
!f>#ifdef HAVE_SSE_INTRINSICS
!f> interface
!f>   subroutine hexa_hh_trafo_real_sse_6hv_single(q, hh, pnb, pnq, pldq, pldh) &
!f>                                bind(C, name="hexa_hh_trafo_real_SSE_6hv_single")
!f>        use, intrinsic :: iso_c_binding
!f>        integer(kind=c_int)        :: pnb, pnq, pldq, pldh
!f>        type(c_ptr), value        :: q
!f>        real(kind=c_float)        :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/
/*
!f>#ifdef HAVE_SPARC64_SSE
!f> interface
!f>   subroutine hexa_hh_trafo_real_sparc64_6hv_single(q, hh, pnb, pnq, pldq, pldh) &
!f>                                bind(C, name="hexa_hh_trafo_real_SPARC64_6hv_single")
!f>        use, intrinsic :: iso_c_binding
!f>        integer(kind=c_int)        :: pnb, pnq, pldq, pldh
!f>        type(c_ptr), value        :: q
!f>        real(kind=c_float)        :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/

647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
/*
!f>#if defined(HAVE_AVX) || defined(HAVE_AVX2)
!f> interface
!f>   subroutine hexa_hh_trafo_real_AVX_AVX2_6hv_double(q, hh, pnb, pnq, pldq, pldh) &
!f>                             bind(C, name="hexa_hh_trafo_real_AVX_AVX2_6hv_double")
!f>     use, intrinsic :: iso_c_binding
!f>     integer(kind=c_int)     :: pnb, pnq, pldq, pldh
!f>     type(c_ptr), value      :: q
!f>     real(kind=c_double)     :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/
/*
!f>#if defined(HAVE_AVX) || defined(HAVE_AVX2)
!f> interface
!f>   subroutine hexa_hh_trafo_real_AVX_AVX2_6hv_single(q, hh, pnb, pnq, pldq, pldh) &
!f>                             bind(C, name="hexa_hh_trafo_real_AVX_AVX2_6hv_single")
!f>     use, intrinsic :: iso_c_binding
!f>     integer(kind=c_int)     :: pnb, pnq, pldq, pldh
!f>     type(c_ptr), value      :: q
!f>     real(kind=c_float)      :: hh(pnb,6)
!f>   end subroutine
!f> end interface
!f>#endif
*/


675
void CONCAT_7ARGS(PREFIX,_hh_trafo_real_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA_TYPE_PTR q, DATA_TYPE_PTR hh, int* pnb, int* pnq, int* pldq, int* pldh)
676
677
678
679
680
681
682
683
{
  int i;
  int nb = *pnb;
  int nq = *pldq;
  int ldq = *pldq;
  int ldh = *pldh;
  int worked_on;

684
685
  worked_on = 0;

686
687
688
#ifdef BLOCK2
  // calculating scalar product to compute
  // 2 householder vectors simultaneously
689
  DATA_TYPE s = hh[(ldh)+1]*1.0;
690
691
692
693
694
#endif

#ifdef BLOCK4
  // calculating scalar products to compute
  // 4 householder vectors simultaneously
695
696
697
698
699
700
701
  DATA_TYPE s_1_2 = hh[(ldh)+1];  
  DATA_TYPE s_1_3 = hh[(ldh*2)+2];
  DATA_TYPE s_2_3 = hh[(ldh*2)+1];
  DATA_TYPE s_1_4 = hh[(ldh*3)+3];
  DATA_TYPE s_2_4 = hh[(ldh*3)+2];
  DATA_TYPE s_3_4 = hh[(ldh*3)+1];

702
703
  // calculate scalar product of first and fourth householder Vector
  // loop counter = 2
704
705
706
  s_1_2 += hh[2-1] * hh[(2+ldh)];          
  s_2_3 += hh[(ldh)+2-1] * hh[2+(ldh*2)];  
  s_3_4 += hh[(ldh*2)+2-1] * hh[2+(ldh*3)];
707
708

  // loop counter = 3
709
710
711
  s_1_2 += hh[3-1] * hh[(3+ldh)];          
  s_2_3 += hh[(ldh)+3-1] * hh[3+(ldh*2)];  
  s_3_4 += hh[(ldh*2)+3-1] * hh[3+(ldh*3)];
712

713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
  s_1_3 += hh[3-2] * hh[3+(ldh*2)];        
  s_2_4 += hh[(ldh*1)+3-2] * hh[3+(ldh*3)];
#endif /* BLOCK4 */

#ifdef BLOCK6
  // calculating scalar products to compute
  // 6 householder vectors simultaneously
  DATA_TYPE scalarprods[15];

  scalarprods[0] = hh[(ldh+1)];  
  scalarprods[1] = hh[(ldh*2)+2];
  scalarprods[2] = hh[(ldh*2)+1];
  scalarprods[3] = hh[(ldh*3)+3];
  scalarprods[4] = hh[(ldh*3)+2];
  scalarprods[5] = hh[(ldh*3)+1];
  scalarprods[6] = hh[(ldh*4)+4];
  scalarprods[7] = hh[(ldh*4)+3];
  scalarprods[8] = hh[(ldh*4)+2];
  scalarprods[9] = hh[(ldh*4)+1];
  scalarprods[10] = hh[(ldh*5)+5];
  scalarprods[11] = hh[(ldh*5)+4];
  scalarprods[12] = hh[(ldh*5)+3];
  scalarprods[13] = hh[(ldh*5)+2];
  scalarprods[14] = hh[(ldh*5)+1];

  // calculate scalar product of first and fourth householder Vector
  // loop counter = 2
  scalarprods[0] += hh[1] * hh[(2+ldh)];           
  scalarprods[2] += hh[(ldh)+1] * hh[2+(ldh*2)];   
  scalarprods[5] += hh[(ldh*2)+1] * hh[2+(ldh*3)]; 
  scalarprods[9] += hh[(ldh*3)+1] * hh[2+(ldh*4)]; 
  scalarprods[14] += hh[(ldh*4)+1] * hh[2+(ldh*5)];

  // loop counter = 3
  scalarprods[0] += hh[2] * hh[(3+ldh)];          
  scalarprods[2] += hh[(ldh)+2] * hh[3+(ldh*2)];  
  scalarprods[5] += hh[(ldh*2)+2] * hh[3+(ldh*3)];
  scalarprods[9] += hh[(ldh*3)+2] * hh[3+(ldh*4)];
  scalarprods[14] += hh[(ldh*4)+2] * hh[3+(ldh*5)];

  scalarprods[1] += hh[1] * hh[3+(ldh*2)];         
  scalarprods[4] += hh[(ldh*1)+1] * hh[3+(ldh*3)]; 
  scalarprods[8] += hh[(ldh*2)+1] * hh[3+(ldh*4)]; 
  scalarprods[13] += hh[(ldh*3)+1] * hh[3+(ldh*5)];

  // loop counter = 4
  scalarprods[0] += hh[3] * hh[(4+ldh)];           
  scalarprods[2] += hh[(ldh)+3] * hh[4+(ldh*2)];   
  scalarprods[5] += hh[(ldh*2)+3] * hh[4+(ldh*3)]; 
  scalarprods[9] += hh[(ldh*3)+3] * hh[4+(ldh*4)]; 
  scalarprods[14] += hh[(ldh*4)+3] * hh[4+(ldh*5)];

  scalarprods[1] += hh[2] * hh[4+(ldh*2)];         
  scalarprods[4] += hh[(ldh*1)+2] * hh[4+(ldh*3)]; 
  scalarprods[8] += hh[(ldh*2)+2] * hh[4+(ldh*4)]; 
  scalarprods[13] += hh[(ldh*3)+2] * hh[4+(ldh*5)];

  scalarprods[3] += hh[1] * hh[4+(ldh*3)];         
  scalarprods[7] += hh[(ldh)+1] * hh[4+(ldh*4)];   
  scalarprods[12] += hh[(ldh*2)+1] * hh[4+(ldh*5)];

  // loop counter = 5
  scalarprods[0] += hh[4] * hh[(5+ldh)];           
  scalarprods[2] += hh[(ldh)+4] * hh[5+(ldh*2)];   
  scalarprods[5] += hh[(ldh*2)+4] * hh[5+(ldh*3)]; 
  scalarprods[9] += hh[(ldh*3)+4] * hh[5+(ldh*4)]; 
  scalarprods[14] += hh[(ldh*4)+4] * hh[5+(ldh*5)];

  scalarprods[1] += hh[3] * hh[5+(ldh*2)];         
  scalarprods[4] += hh[(ldh*1)+3] * hh[5+(ldh*3)]; 
  scalarprods[8] += hh[(ldh*2)+3] * hh[5+(ldh*4)]; 
  scalarprods[13] += hh[(ldh*3)+3] * hh[5+(ldh*5)];

  scalarprods[3] += hh[2] * hh[5+(ldh*3)];         
  scalarprods[7] += hh[(ldh)+2] * hh[5+(ldh*4)];   
  scalarprods[12] += hh[(ldh*2)+2] * hh[5+(ldh*5)];

  scalarprods[6] += hh[1] * hh[5+(ldh*4)];         
  scalarprods[11] += hh[(ldh)+1] * hh[5+(ldh*5)];  


#endif /* BLOCK6 */
795

796
#if VEC_SET == 128 || VEC_SET == 256
797
798
799
800
801
802
803
804
  #pragma ivdep
#endif
  for (i = BLOCK; i < nb; i++)
    {
#ifdef BLOCK2
      s += hh[i-1] * hh[(i+ldh)];
#endif
#ifdef BLOCK4
805
806
807
      s_1_2 += hh[i-1] * hh[(i+ldh)];           
      s_2_3 += hh[(ldh)+i-1] * hh[i+(ldh*2)];   
      s_3_4 += hh[(ldh*2)+i-1] * hh[i+(ldh*3)]; 
808

809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
      s_1_3 += hh[i-2] * hh[i+(ldh*2)];         
      s_2_4 += hh[(ldh*1)+i-2] * hh[i+(ldh*3)]; 

      s_1_4 += hh[i-3] * hh[i+(ldh*3)];         
#endif /* BLOCK4 */
#ifdef BLOCK6
      scalarprods[0] += hh[i-1] * hh[(i+ldh)];           
      scalarprods[2] += hh[(ldh)+i-1] * hh[i+(ldh*2)];   
      scalarprods[5] += hh[(ldh*2)+i-1] * hh[i+(ldh*3)]; 
      scalarprods[9] += hh[(ldh*3)+i-1] * hh[i+(ldh*4)]; 
      scalarprods[14] += hh[(ldh*4)+i-1] * hh[i+(ldh*5)];

      scalarprods[1] += hh[i-2] * hh[i+(ldh*2)];         
      scalarprods[4] += hh[(ldh*1)+i-2] * hh[i+(ldh*3)]; 
      scalarprods[8] += hh[(ldh*2)+i-2] * hh[i+(ldh*4)]; 
      scalarprods[13] += hh[(ldh*3)+i-2] * hh[i+(ldh*5)];

      scalarprods[3] += hh[i-3] * hh[i+(ldh*3)];         
      scalarprods[7] += hh[(ldh)+i-3] * hh[i+(ldh*4)];   
      scalarprods[12] += hh[(ldh*2)+i-3] * hh[i+(ldh*5)];

      scalarprods[6] += hh[i-4] * hh[i+(ldh*4)];         
      scalarprods[11] += hh[(ldh)+i-4] * hh[i+(ldh*5)];  

      scalarprods[10] += hh[i-5] * hh[i+(ldh*5)];        
#endif /* BLOCK6 */
835
836
837
838

    }

  // Production level kernel calls with padding
839
840
#ifdef BLOCK2

841
#if  VEC_SET == 128 || VEC_SET == 1281
842
#ifdef DOUBLE_PRECISION_REAL
843
844
845
#define STEP_SIZE 12
#define ROW_LENGTH 12
#define UPPER_BOUND 10
846
847
#endif
#ifdef SINGLE_PRECISION_REAL
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
#define STEP_SIZE 24
#define ROW_LENGTH 24
#define UPPER_BOUND 20
#endif
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */

#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define STEP_SIZE 24
#define ROW_LENGTH 24
#define UPPER_BOUND 20
#endif
#ifdef SINGLE_PRECISION_REAL
#define STEP_SIZE 48
#define ROW_LENGTH 48
#define UPPER_BOUND 40
#endif
865
#endif /*  VEC_SET == 256 */
866
867

  for (i = 0; i < nq - UPPER_BOUND; i+= STEP_SIZE )
868
    {
869
870
      CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_2hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, s);
      worked_on += ROW_LENGTH;
871
872
873
874
875
876
877
    }

  if (nq == i)
    {
      return;
    }

878
879
#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
880
#ifdef DOUBLE_PRECISION_REAL
881
#define ROW_LENGTH 10
882
883
#endif
#ifdef SINGLE_PRECISION_REAL
884
#define ROW_LENGTH 20
885
#endif
886
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */
887

888
#if  VEC_SET == 256
889
#ifdef DOUBLE_PRECISION_REAL
890
#define ROW_LENGTH 20
891
892
#endif
#ifdef SINGLE_PRECISION_REAL
893
#define ROW_LENGTH 40
894
#endif
895
#endif /* VEC_SET == 256 */
896

897
  if (nq-i == ROW_LENGTH)
898
    {
899
900
      CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_2hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, s);
      worked_on += ROW_LENGTH;
901
    }
902
903
904
905
906

#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 8
907
#endif
908
909
910
911
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 16
#endif
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */
912

913
914
915
916
#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 16
#endif
917
#ifdef SINGLE_PRECISION_REAL
918
919
920
921
922
#define ROW_LENGTH 32
#endif
#endif /* VEC_SET == 256 */

  if (nq-i == ROW_LENGTH)
923
    {
924
925
      CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_2hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, s);
      worked_on += ROW_LENGTH;
926
    }
927
928
929
930
931

#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 6
932
#endif
933
934
935
936
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 12
#endif
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */
937

938
#if  VEC_SET == 256
939
#ifdef DOUBLE_PRECISION_REAL
940
941
942
943
944
945
946
947
948
#define ROW_LENGTH 12
#endif
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 24
#endif
#endif /* VEC_SET == 256 */


  if (nq-i == ROW_LENGTH)
949
    {
950
951
      CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_2hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, s);
      worked_on += ROW_LENGTH;
952
953
    }

954
955
956
957
958
#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 4
#endif
959
#ifdef SINGLE_PRECISION_REAL
960
#define ROW_LENGTH 8
961
#endif
962
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */
963

964
#if  VEC_SET == 256
965
#ifdef DOUBLE_PRECISION_REAL
966
967
968
969
970
971
972
973
974
#define ROW_LENGTH 8
#endif
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 16
#endif
#endif /* VEC_SET == 256 */


  if (nq-i == ROW_LENGTH)
975
    {
976
977
      CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_2hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, s);
      worked_on += ROW_LENGTH;
978
    }
979
980
981
982
983
984
985
986

#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 2
#endif
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 4
987
#endif
988
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */
989

990
991
992
993
#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 4
#endif
994
#ifdef SINGLE_PRECISION_REAL
995
996
997
998
999
#define ROW_LENGTH 8
#endif
#endif /* VEC_SET == 256 */

  if (nq-i == ROW_LENGTH)
1000
    {
1001
1002
      CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_2hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, s);
      worked_on += ROW_LENGTH;
1003
1004
1005
1006
1007
    }

#endif /* BLOCK2 */

#ifdef BLOCK4
1008
1009
1010
1011


#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
1012
#ifdef DOUBLE_PRECISION_REAL
1013
1014
1015
1016
1017
1018
1019
1020
#define ROW_LENGTH 6
#define STEP_SIZE 6
#define UPPER_BOUND 4
#endif
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 12
#define STEP_SIZE 12
#define UPPER_BOUND 8
1021
#endif
1022
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */
1023

1024
1025
1026
1027
1028
1029
#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 12
#define STEP_SIZE 12
#define UPPER_BOUND 8
#endif
1030
#ifdef SINGLE_PRECISION_REAL
1031
1032
1033
1034
1035
1036
1037
#define ROW_LENGTH 24
#define STEP_SIZE 24
#define UPPER_BOUND 16
#endif
#endif /* VEC_SET == 256 */

  for (i = 0; i < nq - UPPER_BOUND; i+= STEP_SIZE )
1038
    {
1039
1040
      CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_4hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, s_1_2, s_1_3, s_2_3, s_1_4, s_2_4, s_3_4);
      worked_on += ROW_LENGTH;
1041
1042
1043
1044
1045
1046
1047
    }

  if (nq == i)
    {
      return;
    }

1048
1049
1050

#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
1051
#ifdef DOUBLE_PRECISION_REAL
1052
1053
1054
1055
#define ROW_LENGTH 4
#endif
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 8
1056
#endif
1057
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */
1058

1059
1060
1061
1062
#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 8
#endif
1063
#ifdef SINGLE_PRECISION_REAL
1064
1065
1066
1067
1068
#define ROW_LENGTH 16
#endif
#endif /* VEC_SET == 256 */

  if (nq-i == ROW_LENGTH )
1069
    {
1070
1071
      CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_4hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, s_1_2, s_1_3, s_2_3, s_1_4, s_2_4, s_3_4);
      worked_on += ROW_LENGTH;
1072
1073
    }

1074
1075
#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
1076
#ifdef DOUBLE_PRECISION_REAL
1077
#define ROW_LENGTH 2
1078
#endif
1079
1080
1081
1082
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 4
#endif
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */
1083

1084
1085
1086
1087
#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 4
#endif
1088
#ifdef SINGLE_PRECISION_REAL
1089
#define ROW_LENGTH 8
1090
#endif
1091
1092
1093
1094
1095
1096
1097
#endif /* VEC_SET == 256 */

   if (nq-i == ROW_LENGTH )
     {
       CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_4hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, s_1_2, s_1_3, s_2_3, s_1_4, s_2_4, s_3_4);
       worked_on += ROW_LENGTH;
     }
1098
1099
1100

#endif /* BLOCK4 */

1101
#ifdef BLOCK6
1102
1103
1104

#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
1105
#ifdef DOUBLE_PRECISION_REAL
1106
1107
1108
#define ROW_LENGTH 4
#define STEP_SIZE 4
#define UPPER_BOUND 2
1109
1110
#endif
#ifdef SINGLE_PRECISION_REAL
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
#define ROW_LENGTH 8
#define STEP_SIZE 8
#define UPPER_BOUND 4
#endif
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */

#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 8
#define STEP_SIZE 8
#define UPPER_BOUND 4
#endif
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 16
#define STEP_SIZE 16
#define UPPER_BOUND 8
1127
#endif
1128
1129
1130
1131
1132
1133
1134
#endif /* VEC_SET == 256 */

  for (i = 0; i < nq - UPPER_BOUND; i+= STEP_SIZE)
    { 
      CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_6hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, scalarprods);
      worked_on += ROW_LENGTH;
    }
1135
1136
1137
1138
    if (nq == i)
      {
        return;
      }
1139
1140
1141

#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
1142
#ifdef DOUBLE_PRECISION_REAL
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
#define ROW_LENGTH 2
#endif
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 4
#endif
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */

#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 4
1153
1154
#endif
#ifdef SINGLE_PRECISION_REAL
1155
1156
1157
1158
1159
#define ROW_LENGTH 8
#endif
#endif /* VEC_SET == 256 */

    if (nq -i == ROW_LENGTH )
1160
      {
1161
1162
        CONCAT_6ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_6hv_,WORD_LENGTH) (&q[i], hh, nb, ldq, ldh, scalarprods);
        worked_on += ROW_LENGTH;
1163
1164
1165
1166
      }
  
#endif /* BLOCK6 */

1167
1168
1169
#ifdef WITH_DEBUG
  if (worked_on != nq)
    {
1170
      printf("Error in real SIMD_SET BLOCK BLOCK kernel %d %d\n", worked_on, nq);
1171
1172
1173
1174
1175
      abort();
    }
#endif
}

1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
#undef ROW_LENGTH
#if  VEC_SET == 128 || VEC_SET == 1281
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 12
#endif
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 24
#endif
#endif /*  VEC_SET == 128 || VEC_SET == 1281 */

#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
#define ROW_LENGTH 24
#endif
#ifdef SINGLE_PRECISION_REAL
#define ROW_LENGTH 48
#endif
#endif /* VEC_SET == 256 */
1194
1195
/*
 * Unrolled kernel that computes
1196
 * ROW_LENGTH rows of Q simultaneously, a
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
 * matrix Vector product with two householder
 */
#ifdef BLOCK2
/*
 * vectors + a rank 2 update is performed
 */
#endif
#ifdef BLOCK4
/*
 * vectors + a rank 1 update is performed
 */
#endif
1209
__forceinline void CONCAT_8ARGS(hh_trafo_kernel_,ROW_LENGTH,_,SIMD_SET,_,BLOCK,hv_,WORD_LENGTH) (DATA_TYPE_PTR q, DATA_TYPE_PTR hh, int nb, int ldq, int ldh,
1210
#ifdef BLOCK2
1211
               DATA_TYPE s)
1212
1213
#endif
#ifdef BLOCK4
1214
1215
1216
1217
               DATA_TYPE s_1_2, DATA_TYPE s_1_3, DATA_TYPE s_2_3, DATA_TYPE s_1_4, DATA_TYPE s_2_4, DATA_TYPE s_3_4)
#endif 
#ifdef BLOCK6
               DATA_TYPE_PTR scalarprods)
1218
1219
1220
1221
1222
1223
1224
1225
#endif
  {
#ifdef BLOCK2
    /////////////////////////////////////////////////////
    // Matrix Vector Multiplication, Q [10 x nb+1] * hh
    // hh contains two householder vectors, with offset 1
    /////////////////////////////////////////////////////
#endif
1226
#if defined(BLOCK4) || defined(BLOCK6)
1227
1228
1229
1230
1231
1232
1233
1234
1235
    /////////////////////////////////////////////////////
    // Matrix Vector Multiplication, Q [10 x nb+3] * hh
    // hh contains four householder vectors
    /////////////////////////////////////////////////////
#endif

    int i;

#ifdef BLOCK2
1236
#if VEC_SET == 128
1237
1238
    // Needed bit mask for floating point sign flip
#ifdef DOUBLE_PRECISION_REAL
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
    __SIMD_DATATYPE sign = (__SIMD_DATATYPE)_mm_set1_epi64x(0x8000000000000000LL);
#endif
#ifdef SINGLE_PRECISION_REAL
    __SIMD_DATATYPE sign = _mm_castsi128_ps(_mm_set_epi32(0x80000000, 0x80000000, 0x80000000, 0x80000000));
#endif
#endif /* HAVE_SSE_INTRINSICS */

#if  VEC_SET == 256
#ifdef DOUBLE_PRECISION_REAL
        __SIMD_DATATYPE sign = (__SIMD_DATATYPE)_mm256_set1_epi64x(0x8000000000000000);
1249
1250
#endif
#ifdef SINGLE_PRECISION_REAL
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
        __SIMD_DATATYPE sign = (__SIMD_DATATYPE)_mm256_set1_epi32(0x80000000);
#endif
#endif /* VEC_SET == 256 */

    __SIMD_DATATYPE x1 = _SIMD_LOAD(&q[ldq]);
    __SIMD_DATATYPE x2 = _SIMD_LOAD(&q[ldq+offset]);
    __SIMD_DATATYPE x3 = _SIMD_LOAD(&q[ldq+2*offset]);
    __SIMD_DATATYPE x4 = _SIMD_LOAD(&q[ldq+3*offset]);
    __SIMD_DATATYPE x5 = _SIMD_LOAD(&q[ldq+4*offset]);
    __SIMD_DATATYPE x6 = _SIMD_LOAD(&q[ldq+5*offset]);

#if VEC_SET == 128
    __SIMD_DATATYPE h1 = _SSE_SET1(hh[ldh+1]);
#endif
#if VEC_SET == 1281
    __SIMD_DATATYPE h1 = _SSE_SET(hh[ldh+1], hh[ldh+1]);
#endif
#if VEC_SET == 256
    __SIMD_DATATYPE h1 = _SIMD_BROADCAST(&hh[ldh+1]);
#endif
 
    __SIMD_DATATYPE h2;
#ifdef __ELPA_USE_FMA__
    __SIMD_DATATYPE q1 = _SIMD_LOAD(q);
    __SIMD_DATATYPE y1 = _SIMD_FMA(x1, h1, q1);
    __SIMD_DATATYPE q2 = _SIMD_LOAD(&q[offset]);
    __SIMD_DATATYPE y2 = _SIMD_FMA(x2, h1, q2);
    __SIMD_DATATYPE q3 = _SIMD_LOAD(&q[2*offset]);
    __SIMD_DATATYPE y3 = _SIMD_FMA(x3, h1, q3);
    __SIMD_DATATYPE q4 = _SIMD_LOAD(&q[3*offset]);
    __SIMD_DATATYPE y4 = _SIMD_FMA(x4, h1, q4);
    __SIMD_DATATYPE q5 = _SIMD_LOAD(&q[4*offset]);
    __SIMD_DATATYPE y5 = _SIMD_FMA(x5, h1, q5);
    __SIMD_DATATYPE q6 = _SIMD_LOAD(&q[5*offset]);
    __SIMD_DATATYPE y6 = _SIMD_FMA(x6, h1, q6);
#else
    __SIMD_DATATYPE q1 = _SIMD_LOAD(q);
    __SIMD_DATATYPE y1 = _SIMD_ADD(q1, _SIMD_MUL(x1, h1));
    __SIMD_DATATYPE q2 = _SIMD_LOAD(&q[offset]);
    __SIMD_DATATYPE y2 = _SIMD_ADD(q2, _SIMD_MUL(x2, h1));
    __SIMD_DATATYPE q3 = _SIMD_LOAD(&q[2*offset]);
    __SIMD_DATATYPE y3 = _SIMD_ADD(q3, _SIMD_MUL(x3, h1));
    __SIMD_DATATYPE q4 = _SIMD_LOAD(&q[3*offset]);
    __SIMD_DATATYPE y4 = _SIMD_ADD(q4, _SIMD_MUL(x4, h1));
    __SIMD_DATATYPE q5 = _SIMD_LOAD(&q[4*offset]);
    __SIMD_DATATYPE y5 = _SIMD_ADD(q5, _SIMD_MUL(x5, h1));
    __SIMD_DATATYPE q6 = _SIMD_LOAD(&q[5*offset]);
    __SIMD_DATATYPE y6 = _SIMD_ADD(q6, _SIMD_MUL(x6, h1));
#endif
1300
1301
1302
#endif /* BLOCK2 */

#ifdef BLOCK4
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
    __SIMD_DATATYPE a1_1 = _SIMD_LOAD(&q[ldq*3]);
    __SIMD_DATATYPE a2_1 = _SIMD_LOAD(&q[ldq*2]);
    __SIMD_DATATYPE a3_1 = _SIMD_LOAD(&q[ldq]);  
    __SIMD_DATATYPE a4_1 = _SIMD_LOAD(&q[0]);    

#if VEC_SET == 128
    __SIMD_DATATYPE h_2_1 = _SSE_SET1(hh[ldh+1]);    
    __SIMD_DATATYPE h_3_2 = _SSE_SET1(hh[(ldh*2)+1]);
    __SIMD_DATATYPE h_3_1 = _SSE_SET1(hh[(ldh*2)+2]);
    __SIMD_DATATYPE h_4_3 = _SSE_SET1(hh[(ldh*3)+1]);
    __SIMD_DATATYPE h_4_2 = _SSE_SET1(hh[(ldh*3)+2]);
    __SIMD_DATATYPE h_4_1 = _SSE_SET1(hh[(ldh*3)+3]);
#endif

#if VEC_SET == 1281
    __SIMD_DATATYPE h_2_1 = _SSE_SET(hh[ldh+1], hh[ldh+1]);
    __SIMD_DATATYPE h_3_2 = _SSE_SET(hh[(ldh*2)+1], hh[(ldh*2)+1]);
    __SIMD_DATATYPE h_3_1 = _SSE_SET(hh[(ldh*2)+2], hh[(ldh*2)+2]);
    __SIMD_DATATYPE h_4_3 = _SSE_SET(hh[(ldh*3)+1], hh[(ldh*3)+1]);
    __SIMD_DATATYPE h_4_2 = _SSE_SET(hh[(ldh*3)+2], hh[(ldh*3)+2]);
    __SIMD_DATATYPE h_4_1 = _SSE_SET(hh[(ldh*3)+3], hh[(ldh*3)+3]);
#endif

1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
#if VEC_SET == 256
    __SIMD_DATATYPE h_2_1 = _SIMD_BROADCAST(&hh[ldh+1]);
    __SIMD_DATATYPE h_3_2 = _SIMD_BROADCAST(&hh[(ldh*2)+1]);
    __SIMD_DATATYPE h_3_1 = _SIMD_BROADCAST(&hh[(ldh*2)+2]);
    __SIMD_DATATYPE h_4_3 = _SIMD_BROADCAST(&hh[(ldh*3)+1]);
    __SIMD_DATATYPE h_4_2 = _SIMD_BROADCAST(&hh[(ldh*3)+2]);
    __SIMD_DATATYPE h_4_1 = _SIMD_BROADCAST(&hh[(ldh*3)+3]);
#endif

#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE w1 = _SIMD_FMA(a3_1, h_4_3, a4_1);
    w1 = _SIMD_FMA(a2_1, h_4_2, w1);
    w1 = _SIMD_FMA(a1_1, h_4_1, w1);
    register __SIMD_DATATYPE z1 = _SIMD_FMA(a2_1, h_3_2, a3_1);
    z1 = _SIMD_FMA(a1_1, h_3_1, z1);
    register __SIMD_DATATYPE y1 = _SIMD_FMA(a1_1, h_2_1, a2_1);
    register __SIMD_DATATYPE x1 = a1_1;
#else
1344
1345
1346
1347
1348
1349
1350
    register __SIMD_DATATYPE w1 = _SIMD_ADD(a4_1, _SIMD_MUL(a3_1, h_4_3));
    w1 = _SIMD_ADD(w1, _SIMD_MUL(a2_1, h_4_2));                          
    w1 = _SIMD_ADD(w1, _SIMD_MUL(a1_1, h_4_1));                          
    register __SIMD_DATATYPE z1 = _SIMD_ADD(a3_1, _SIMD_MUL(a2_1, h_3_2));
    z1 = _SIMD_ADD(z1, _SIMD_MUL(a1_1, h_3_1));                          
    register __SIMD_DATATYPE y1 = _SIMD_ADD(a2_1, _SIMD_MUL(a1_1, h_2_1));
    register __SIMD_DATATYPE x1 = a1_1;
1351
#endif /* __ELPA_USE_FMA__ */
1352
1353
1354
1355
1356
1357

    __SIMD_DATATYPE a1_2 = _SIMD_LOAD(&q[(ldq*3)+offset]);                  
    __SIMD_DATATYPE a2_2 = _SIMD_LOAD(&q[(ldq*2)+offset]);
    __SIMD_DATATYPE a3_2 = _SIMD_LOAD(&q[ldq+offset]);
    __SIMD_DATATYPE a4_2 = _SIMD_LOAD(&q[0+offset]);

1358
1359
1360
1361
1362
1363
1364
1365
1366
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE w2 = _SIMD_FMA(a3_2, h_4_3, a4_2);
    w2 = _SIMD_FMA(a2_2, h_4_2, w2);
    w2 = _SIMD_FMA(a1_2, h_4_1, w2);
    register __SIMD_DATATYPE z2 = _SIMD_FMA(a2_2, h_3_2, a3_2);
    z2 = _SIMD_FMA(a1_2, h_3_1, z2);
    register __SIMD_DATATYPE y2 = _SIMD_FMA(a1_2, h_2_1, a2_2);
    register __SIMD_DATATYPE x2 = a1_2;
#else
1367
1368
1369
1370
1371
1372
1373
    register __SIMD_DATATYPE w2 = _SIMD_ADD(a4_2, _SIMD_MUL(a3_2, h_4_3));
    w2 = _SIMD_ADD(w2, _SIMD_MUL(a2_2, h_4_2));
    w2 = _SIMD_ADD(w2, _SIMD_MUL(a1_2, h_4_1));
    register __SIMD_DATATYPE z2 = _SIMD_ADD(a3_2, _SIMD_MUL(a2_2, h_3_2));
    z2 = _SIMD_ADD(z2, _SIMD_MUL(a1_2, h_3_1));
    register __SIMD_DATATYPE y2 = _SIMD_ADD(a2_2, _SIMD_MUL(a1_2, h_2_1));
    register __SIMD_DATATYPE x2 = a1_2;
1374
#endif /* __ELPA_USE_FMA__ */
1375
1376
1377
1378
1379
1380

    __SIMD_DATATYPE a1_3 = _SIMD_LOAD(&q[(ldq*3)+2*offset]);
    __SIMD_DATATYPE a2_3 = _SIMD_LOAD(&q[(ldq*2)+2*offset]);
    __SIMD_DATATYPE a3_3 = _SIMD_LOAD(&q[ldq+2*offset]);
    __SIMD_DATATYPE a4_3 = _SIMD_LOAD(&q[0+2*offset]);

1381
1382
1383
1384
1385
1386
1387
1388
1389
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE w3 = _SIMD_FMA(a3_3, h_4_3, a4_3);
    w3 = _SIMD_FMA(a2_3, h_4_2, w3);
    w3 = _SIMD_FMA(a1_3, h_4_1, w3);
    register __SIMD_DATATYPE z3 = _SIMD_FMA(a2_3, h_3_2, a3_3);
    z3 = _SIMD_FMA(a1_3, h_3_1, z3);
    register __SIMD_DATATYPE y3 = _SIMD_FMA(a1_3, h_2_1, a2_3);
    register __SIMD_DATATYPE x3 = a1_3;
#else
1390
1391
1392
1393
1394
1395
1396
    register __SIMD_DATATYPE w3 = _SIMD_ADD(a4_3, _SIMD_MUL(a3_3, h_4_3));
    w3 = _SIMD_ADD(w3, _SIMD_MUL(a2_3, h_4_2));
    w3 = _SIMD_ADD(w3, _SIMD_MUL(a1_3, h_4_1));
    register __SIMD_DATATYPE z3 = _SIMD_ADD(a3_3, _SIMD_MUL(a2_3, h_3_2));
    z3 = _SIMD_ADD(z3, _SIMD_MUL(a1_3, h_3_1));
    register __SIMD_DATATYPE y3 = _SIMD_ADD(a2_3, _SIMD_MUL(a1_3, h_2_1));
    register __SIMD_DATATYPE x3 = a1_3;
1397
#endif /* __ELPA_USE_FMA__ */
1398
1399
1400
1401
1402
1403

    __SIMD_DATATYPE a1_4 = _SIMD_LOAD(&q[(ldq*3)+3*offset]);
    __SIMD_DATATYPE a2_4 = _SIMD_LOAD(&q[(ldq*2)+3*offset]);
    __SIMD_DATATYPE a3_4 = _SIMD_LOAD(&q[ldq+3*offset]);
    __SIMD_DATATYPE a4_4 = _SIMD_LOAD(&q[0+3*offset]);

1404
1405
1406
1407
1408
1409
1410
1411
1412
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE w4 = _SIMD_FMA(a3_4, h_4_3, a4_4);
    w4 = _SIMD_FMA(a2_4, h_4_2, w4);
    w4 = _SIMD_FMA(a1_4, h_4_1, w4);
    register __SIMD_DATATYPE z4 = _SIMD_FMA(a2_4, h_3_2, a3_4);
    z4 = _SIMD_FMA(a1_4, h_3_1, z4);
    register __SIMD_DATATYPE y4 = _SIMD_FMA(a1_4, h_2_1, a2_4);
    register __SIMD_DATATYPE x4 = a1_4;
#else
1413
1414
1415
1416
1417
1418
1419
    register __SIMD_DATATYPE w4 = _SIMD_ADD(a4_4, _SIMD_MUL(a3_4, h_4_3));
    w4 = _SIMD_ADD(w4, _SIMD_MUL(a2_4, h_4_2));
    w4 = _SIMD_ADD(w4, _SIMD_MUL(a1_4, h_4_1));
    register __SIMD_DATATYPE z4 = _SIMD_ADD(a3_4, _SIMD_MUL(a2_4, h_3_2));
    z4 = _SIMD_ADD(z4, _SIMD_MUL(a1_4, h_3_1));
    register __SIMD_DATATYPE y4 = _SIMD_ADD(a2_4, _SIMD_MUL(a1_4, h_2_1));
    register __SIMD_DATATYPE x4 = a1_4;
1420
#endif /* __ELPA_USE_FMA__ */
1421
1422
1423
1424
1425
1426

    __SIMD_DATATYPE a1_5 = _SIMD_LOAD(&q[(ldq*3)+4*offset]);
    __SIMD_DATATYPE a2_5 = _SIMD_LOAD(&q[(ldq*2)+4*offset]);
    __SIMD_DATATYPE a3_5 = _SIMD_LOAD(&q[ldq+4*offset]);
    __SIMD_DATATYPE a4_5 = _SIMD_LOAD(&q[0+4*offset]);

1427
1428
1429
1430
1431
1432
1433
1434
1435
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE w5 = _SIMD_FMA(a3_5, h_4_3, a4_5);
    w5 = _SIMD_FMA(a2_5, h_4_2, w5);
    w5 = _SIMD_FMA(a1_5, h_4_1, w5);
    register __SIMD_DATATYPE z5 = _SIMD_FMA(a2_5, h_3_2, a3_5);
    z5 = _SIMD_FMA(a1_5, h_3_1, z5);
    register __SIMD_DATATYPE y5 = _SIMD_FMA(a1_5, h_2_1, a2_5);
    register __SIMD_DATATYPE x5 = a1_5;
#else
1436
1437
1438
1439
1440
1441
1442
    register __SIMD_DATATYPE w5 = _SIMD_ADD(a4_5, _SIMD_MUL(a3_5, h_4_3));
    w5 = _SIMD_ADD(w5, _SIMD_MUL(a2_5, h_4_2));
    w5 = _SIMD_ADD(w5, _SIMD_MUL(a1_5, h_4_1));
    register __SIMD_DATATYPE z5 = _SIMD_ADD(a3_5, _SIMD_MUL(a2_5, h_3_2));
    z5 = _SIMD_ADD(z5, _SIMD_MUL(a1_5, h_3_1));
    register __SIMD_DATATYPE y5 = _SIMD_ADD(a2_5, _SIMD_MUL(a1_5, h_2_1));
    register __SIMD_DATATYPE x5 = a1_5;
1443
#endif /* __ELPA_USE_FMA__ */
1444
1445
1446
1447
1448
1449

    __SIMD_DATATYPE a1_6 = _SIMD_LOAD(&q[(ldq*3)+5*offset]);
    __SIMD_DATATYPE a2_6 = _SIMD_LOAD(&q[(ldq*2)+5*offset]);
    __SIMD_DATATYPE a3_6 = _SIMD_LOAD(&q[ldq+5*offset]);
    __SIMD_DATATYPE a4_6 = _SIMD_LOAD(&q[0+5*offset]);

1450
1451
1452
1453
1454
1455
1456
1457
1458
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE w6 = _SIMD_FMA(a3_6, h_4_3, a4_6);
    w6 = _SIMD_FMA(a2_6, h_4_2, w6);
    w6 = _SIMD_FMA(a1_6, h_4_1, w6);
    register __SIMD_DATATYPE z6 = _SIMD_FMA(a2_6, h_3_2, a3_6);
    z6 = _SIMD_FMA(a1_6, h_3_1, z6);
    register __SIMD_DATATYPE y6 = _SIMD_FMA(a1_6, h_2_1, a2_6);
    register __SIMD_DATATYPE x6 = a1_6;
#else
1459
1460
1461
1462
1463
1464
1465
    register __SIMD_DATATYPE w6 = _SIMD_ADD(a4_6, _SIMD_MUL(a3_6, h_4_3));
    w6 = _SIMD_ADD(w6, _SIMD_MUL(a2_6, h_4_2));
    w6 = _SIMD_ADD(w6, _SIMD_MUL(a1_6, h_4_1));
    register __SIMD_DATATYPE z6 = _SIMD_ADD(a3_6, _SIMD_MUL(a2_6, h_3_2));
    z6 = _SIMD_ADD(z6, _SIMD_MUL(a1_6, h_3_1));
    register __SIMD_DATATYPE y6 = _SIMD_ADD(a2_6, _SIMD_MUL(a1_6, h_2_1));
    register __SIMD_DATATYPE x6 = a1_6;
1466
#endif /* __ELPA_USE_FMA__ */
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478

    __SIMD_DATATYPE q1;
    __SIMD_DATATYPE q2;
    __SIMD_DATATYPE q3;
    __SIMD_DATATYPE q4;
    __SIMD_DATATYPE q5;
    __SIMD_DATATYPE q6;

    __SIMD_DATATYPE h1;
    __SIMD_DATATYPE h2;
    __SIMD_DATATYPE h3;
    __SIMD_DATATYPE h4;
1479
1480
#endif /* BLOCK4 */

1481
1482
#ifdef BLOCK6
    
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
    __SIMD_DATATYPE a1_1 = _SIMD_LOAD(&q[ldq*5]);
    __SIMD_DATATYPE a2_1 = _SIMD_LOAD(&q[ldq*4]);
    __SIMD_DATATYPE a3_1 = _SIMD_LOAD(&q[ldq*3]);
    __SIMD_DATATYPE a4_1 = _SIMD_LOAD(&q[ldq*2]);
    __SIMD_DATATYPE a5_1 = _SIMD_LOAD(&q[ldq]);  
    __SIMD_DATATYPE a6_1 = _SIMD_LOAD(&q[0]);    

#if VEC_SET == 128
    __SIMD_DATATYPE h_6_5 = _SSE_SET1(hh[(ldh*5)+1]);
    __SIMD_DATATYPE h_6_4 = _SSE_SET1(hh[(ldh*5)+2]);
    __SIMD_DATATYPE h_6_3 = _SSE_SET1(hh[(ldh*5)+3]);
    __SIMD_DATATYPE h_6_2 = _SSE_SET1(hh[(ldh*5)+4]);
    __SIMD_DATATYPE h_6_1 = _SSE_SET1(hh[(ldh*5)+5]);
#endif

#if VEC_SET == 1281
    __SIMD_DATATYPE h_6_5 = _SSE_SET(hh[(ldh*5)+1], hh[(ldh*5)+1]);
    __SIMD_DATATYPE h_6_4 = _SSE_SET(hh[(ldh*5)+2], hh[(ldh*5)+2]);
    __SIMD_DATATYPE h_6_3 = _SSE_SET(hh[(ldh*5)+3], hh[(ldh*5)+3]);
    __SIMD_DATATYPE h_6_2 = _SSE_SET(hh[(ldh*5)+4], hh[(ldh*5)+4]);
    __SIMD_DATATYPE h_6_1 = _SSE_SET(hh[(ldh*5)+5], hh[(ldh*5)+5]);
#endif

1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
#if VEC_SET == 256
    __SIMD_DATATYPE h_6_5 = _SIMD_BROADCAST(&hh[(ldh*5)+1]);
    __SIMD_DATATYPE h_6_4 = _SIMD_BROADCAST(&hh[(ldh*5)+2]);
    __SIMD_DATATYPE h_6_3 = _SIMD_BROADCAST(&hh[(ldh*5)+3]);
    __SIMD_DATATYPE h_6_2 = _SIMD_BROADCAST(&hh[(ldh*5)+4]);
    __SIMD_DATATYPE h_6_1 = _SIMD_BROADCAST(&hh[(ldh*5)+5]);
#endif

#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE t1 = _SIMD_FMA(a5_1, h_6_5, a6_1);
    t1 = _SIMD_FMA(a4_1, h_6_4, t1);
    t1 = _SIMD_FMA(a3_1, h_6_3, t1);
    t1 = _SIMD_FMA(a2_1, h_6_2, t1);
    t1 = _SIMD_FMA(a1_1, h_6_1, t1);
#else
1521
1522
1523
1524
1525
    register __SIMD_DATATYPE t1 = _SIMD_ADD(a6_1, _SIMD_MUL(a5_1, h_6_5)); 
    t1 = _SIMD_ADD(t1, _SIMD_MUL(a4_1, h_6_4));
    t1 = _SIMD_ADD(t1, _SIMD_MUL(a3_1, h_6_3));
    t1 = _SIMD_ADD(t1, _SIMD_MUL(a2_1, h_6_2));
    t1 = _SIMD_ADD(t1, _SIMD_MUL(a1_1, h_6_1));
1526
#endif /* __ELPA_USE_FMA__ */
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541

#if VEC_SET == 128
    __SIMD_DATATYPE h_5_4 = _SSE_SET1(hh[(ldh*4)+1]);
    __SIMD_DATATYPE h_5_3 = _SSE_SET1(hh[(ldh*4)+2]);
    __SIMD_DATATYPE h_5_2 = _SSE_SET1(hh[(ldh*4)+3]);
    __SIMD_DATATYPE h_5_1 = _SSE_SET1(hh[(ldh*4)+4]);
#endif

#if VEC_SET == 1281
    __SIMD_DATATYPE h_5_4 = _SSE_SET(hh[(ldh*4)+1], hh[(ldh*4)+1]);
    __SIMD_DATATYPE h_5_3 = _SSE_SET(hh[(ldh*4)+2], hh[(ldh*4)+2]);
    __SIMD_DATATYPE h_5_2 = _SSE_SET(hh[(ldh*4)+3], hh[(ldh*4)+3]);
    __SIMD_DATATYPE h_5_1 = _SSE_SET(hh[(ldh*4)+4], hh[(ldh*4)+4]);
#endif

1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
#if VEC_SET == 256
    __SIMD_DATATYPE h_5_4 = _SIMD_BROADCAST(&hh[(ldh*4)+1]);
    __SIMD_DATATYPE h_5_3 = _SIMD_BROADCAST(&hh[(ldh*4)+2]);
    __SIMD_DATATYPE h_5_2 = _SIMD_BROADCAST(&hh[(ldh*4)+3]);
    __SIMD_DATATYPE h_5_1 = _SIMD_BROADCAST(&hh[(ldh*4)+4]);
#endif

#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE v1 = _SIMD_FMA(a4_1, h_5_4, a5_1);
    v1 = _SIMD_FMA(a3_1, h_5_3, v1);
    v1 = _SIMD_FMA(a2_1, h_5_2, v1);
    v1 = _SIMD_FMA(a1_1, h_5_1, v1);
#else
1555
1556
1557
1558
    register __SIMD_DATATYPE v1 = _SIMD_ADD(a5_1, _SIMD_MUL(a4_1, h_5_4)); 
    v1 = _SIMD_ADD(v1, _SIMD_MUL(a3_1, h_5_3));
    v1 = _SIMD_ADD(v1, _SIMD_MUL(a2_1, h_5_2));
    v1 = _SIMD_ADD(v1, _SIMD_MUL(a1_1, h_5_1));
1559
#endif /* __ELPA_USE_FMA__ */
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572

#if VEC_SET == 128
    __SIMD_DATATYPE h_4_3 = _SSE_SET1(hh[(ldh*3)+1]);
    __SIMD_DATATYPE h_4_2 = _SSE_SET1(hh[(ldh*3)+2]);
    __SIMD_DATATYPE h_4_1 = _SSE_SET1(hh[(ldh*3)+3]);
#endif

#if VEC_SET == 1281
    __SIMD_DATATYPE h_4_3 = _SSE_SET(hh[(ldh*3)+1], hh[(ldh*3)+1]);
    __SIMD_DATATYPE h_4_2 = _SSE_SET(hh[(ldh*3)+2], hh[(ldh*3)+2]);
    __SIMD_DATATYPE h_4_1 = _SSE_SET(hh[(ldh*3)+3], hh[(ldh*3)+3]);
#endif

1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
#if VEC_SET == 256
    __SIMD_DATATYPE h_4_3 = _SIMD_BROADCAST(&hh[(ldh*3)+1]);
    __SIMD_DATATYPE h_4_2 = _SIMD_BROADCAST(&hh[(ldh*3)+2]);
    __SIMD_DATATYPE h_4_1 = _SIMD_BROADCAST(&hh[(ldh*3)+3]);
#endif

#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE w1 = _SIMD_FMA(a3_1, h_4_3, a4_1);
    w1 = _SIMD_FMA(a2_1, h_4_2, w1);
    w1 = _SIMD_FMA(a1_1, h_4_1, w1);
#else
1584
1585
1586
    register __SIMD_DATATYPE w1 = _SIMD_ADD(a4_1, _SIMD_MUL(a3_1, h_4_3)); 
    w1 = _SIMD_ADD(w1, _SIMD_MUL(a2_1, h_4_2));
    w1 = _SIMD_ADD(w1, _SIMD_MUL(a1_1, h_4_1));
1587
#endif /* __ELPA_USE_FMA__ */
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600

#if VEC_SET == 128
    __SIMD_DATATYPE h_2_1 = _SSE_SET1(hh[ldh+1]);    
    __SIMD_DATATYPE h_3_2 = _SSE_SET1(hh[(ldh*2)+1]);
    __SIMD_DATATYPE h_3_1 = _SSE_SET1(hh[(ldh*2)+2]);
#endif

#if VEC_SET == 1281
    __SIMD_DATATYPE h_2_1 = _SSE_SET(hh[ldh+1], hh[ldh+1]);
    __SIMD_DATATYPE h_3_2 = _SSE_SET(hh[(ldh*2)+1], hh[(ldh*2)+1]);
    __SIMD_DATATYPE h_3_1 = _SSE_SET(hh[(ldh*2)+2], hh[(ldh*2)+2]);
#endif

1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
#if VEC_SET == 256
    __SIMD_DATATYPE h_2_1 = _SIMD_BROADCAST(&hh[ldh+1]);
    __SIMD_DATATYPE h_3_2 = _SIMD_BROADCAST(&hh[(ldh*2)+1]);
    __SIMD_DATATYPE h_3_1 = _SIMD_BROADCAST(&hh[(ldh*2)+2]);
#endif

#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE z1 = _SIMD_FMA(a2_1, h_3_2, a3_1);
    z1 = _SIMD_FMA(a1_1, h_3_1, z1);
    register __SIMD_DATATYPE y1 = _SIMD_FMA(a1_1, h_2_1, a2_1);
#else
1612
1613
1614
    register __SIMD_DATATYPE z1 = _SIMD_ADD(a3_1, _SIMD_MUL(a2_1, h_3_2));
    z1 = _SIMD_ADD(z1, _SIMD_MUL(a1_1, h_3_1));
    register __SIMD_DATATYPE y1 = _SIMD_ADD(a2_1, _SIMD_MUL(a1_1, h_2_1)); 
1615
#endif /* __ELPA_USE_FMA__ */
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625

    register __SIMD_DATATYPE x1 = a1_1;

    __SIMD_DATATYPE a1_2 = _SIMD_LOAD(&q[(ldq*5)+offset]);
    __SIMD_DATATYPE a2_2 = _SIMD_LOAD(&q[(ldq*4)+offset]);
    __SIMD_DATATYPE a3_2 = _SIMD_LOAD(&q[(ldq*3)+offset]);
    __SIMD_DATATYPE a4_2 = _SIMD_LOAD(&q[(ldq*2)+offset]);
    __SIMD_DATATYPE a5_2 = _SIMD_LOAD(&q[(ldq)+offset]);
    __SIMD_DATATYPE a6_2 = _SIMD_LOAD(&q[offset]);

1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE t2 = _SIMD_FMA(a5_2, h_6_5, a6_2);
    t2 = _SIMD_FMA(a4_2, h_6_4, t2);
    t2 = _SIMD_FMA(a3_2, h_6_3, t2);
    t2 = _SIMD_FMA(a2_2, h_6_2, t2);
    t2 = _SIMD_FMA(a1_2, h_6_1, t2);
    register __SIMD_DATATYPE v2 = _SIMD_FMA(a4_2, h_5_4, a5_2);
    v2 = _SIMD_FMA(a3_2, h_5_3, v2);
    v2 = _SIMD_FMA(a2_2, h_5_2, v2);
    v2 = _SIMD_FMA(a1_2, h_5_1, v2);
    register __SIMD_DATATYPE w2 = _SIMD_FMA(a3_2, h_4_3, a4_2);
    w2 = _SIMD_FMA(a2_2, h_4_2, w2);
    w2 = _SIMD_FMA(a1_2, h_4_1, w2);
    register __SIMD_DATATYPE z2 = _SIMD_FMA(a2_2, h_3_2, a3_2);
    z2 = _SIMD_FMA(a1_2, h_3_1, z2);
    register __SIMD_DATATYPE y2 = _SIMD_FMA(a1_2, h_2_1, a2_2);
#else
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
    register __SIMD_DATATYPE t2 = _SIMD_ADD(a6_2, _SIMD_MUL(a5_2, h_6_5));
    t2 = _SIMD_ADD(t2, _SIMD_MUL(a4_2, h_6_4));
    t2 = _SIMD_ADD(t2, _SIMD_MUL(a3_2, h_6_3));
    t2 = _SIMD_ADD(t2, _SIMD_MUL(a2_2, h_6_2));
    t2 = _SIMD_ADD(t2, _SIMD_MUL(a1_2, h_6_1));
    register __SIMD_DATATYPE v2 = _SIMD_ADD(a5_2, _SIMD_MUL(a4_2, h_5_4));
    v2 = _SIMD_ADD(v2, _SIMD_MUL(a3_2, h_5_3));
    v2 = _SIMD_ADD(v2, _SIMD_MUL(a2_2, h_5_2));
    v2 = _SIMD_ADD(v2, _SIMD_MUL(a1_2, h_5_1));
    register __SIMD_DATATYPE w2 = _SIMD_ADD(a4_2, _SIMD_MUL(a3_2, h_4_3));
    w2 = _SIMD_ADD(w2, _SIMD_MUL(a2_2, h_4_2));
    w2 = _SIMD_ADD(w2, _SIMD_MUL(a1_2, h_4_1));
    register __SIMD_DATATYPE z2 = _SIMD_ADD(a3_2, _SIMD_MUL(a2_2, h_3_2));
    z2 = _SIMD_ADD(z2, _SIMD_MUL(a1_2, h_3_1));
    register __SIMD_DATATYPE y2 = _SIMD_ADD(a2_2, _SIMD_MUL(a1_2, h_2_1));
1658
#endif /* __ELPA_USE_FMA__ */
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668

    register __SIMD_DATATYPE x2 = a1_2;

    __SIMD_DATATYPE a1_3 = _SIMD_LOAD(&q[(ldq*5)+2*offset]);
    __SIMD_DATATYPE a2_3 = _SIMD_LOAD(&q[(ldq*4)+2*offset]);
    __SIMD_DATATYPE a3_3 = _SIMD_LOAD(&q[(ldq*3)+2*offset]);
    __SIMD_DATATYPE a4_3 = _SIMD_LOAD(&q[(ldq*2)+2*offset]);
    __SIMD_DATATYPE a5_3 = _SIMD_LOAD(&q[(ldq)+2*offset]);
    __SIMD_DATATYPE a6_3 = _SIMD_LOAD(&q[2*offset]);

1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE t3 = _SIMD_FMA(a5_3, h_6_5, a6_3);
    t3 = _SIMD_FMA(a4_3, h_6_4, t3);
    t3 = _SIMD_FMA(a3_3, h_6_3, t3);
    t3 = _SIMD_FMA(a2_3, h_6_2, t3);
    t3 = _SIMD_FMA(a1_3, h_6_1, t3);
    register __SIMD_DATATYPE v3 = _SIMD_FMA(a4_3, h_5_4, a5_3);
    v3 = _SIMD_FMA(a3_3, h_5_3, v3);
    v3 = _SIMD_FMA(a2_3, h_5_2, v3);
    v3 = _SIMD_FMA(a1_3, h_5_1, v3);
    register __SIMD_DATATYPE w3 = _SIMD_FMA(a3_3, h_4_3, a4_3);
    w3 = _SIMD_FMA(a2_3, h_4_2, w3);
    w3 = _SIMD_FMA(a1_3, h_4_1, w3);
    register __SIMD_DATATYPE z3 = _SIMD_FMA(a2_3, h_3_2, a3_3);
    z3 = _SIMD_FMA(a1_3, h_3_1, z3);
    register __SIMD_DATATYPE y3 = _SIMD_FMA(a1_3, h_2_1, a2_3);
#else
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
    register __SIMD_DATATYPE t3 = _SIMD_ADD(a6_3, _SIMD_MUL(a5_3, h_6_5));
    t3 = _SIMD_ADD(t3, _SIMD_MUL(a4_3, h_6_4));
    t3 = _SIMD_ADD(t3, _SIMD_MUL(a3_3, h_6_3));
    t3 = _SIMD_ADD(t3, _SIMD_MUL(a2_3, h_6_2));
    t3 = _SIMD_ADD(t3, _SIMD_MUL(a1_3, h_6_1));
    register __SIMD_DATATYPE v3 = _SIMD_ADD(a5_3, _SIMD_MUL(a4_3, h_5_4));
    v3 = _SIMD_ADD(v3, _SIMD_MUL(a3_3, h_5_3));
    v3 = _SIMD_ADD(v3, _SIMD_MUL(a2_3, h_5_2));
    v3 = _SIMD_ADD(v3, _SIMD_MUL(a1_3, h_5_1));
    register __SIMD_DATATYPE w3 = _SIMD_ADD(a4_3, _SIMD_MUL(a3_3, h_4_3));
    w3 = _SIMD_ADD(w3, _SIMD_MUL(a2_3, h_4_2));
    w3 = _SIMD_ADD(w3, _SIMD_MUL(a1_3, h_4_1));
    register __SIMD_DATATYPE z3 = _SIMD_ADD(a3_3, _SIMD_MUL(a2_3, h_3_2));
    z3 = _SIMD_ADD(z3, _SIMD_MUL(a1_3, h_3_1));
    register __SIMD_DATATYPE y3 = _SIMD_ADD(a2_3, _SIMD_MUL(a1_3, h_2_1));
1701
#endif /* __ELPA_USE_FMA__ */
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711

    register __SIMD_DATATYPE x3 = a1_3;

    __SIMD_DATATYPE a1_4 = _SIMD_LOAD(&q[(ldq*5)+3*offset]);
    __SIMD_DATATYPE a2_4 = _SIMD_LOAD(&q[(ldq*4)+3*offset]);
    __SIMD_DATATYPE a3_4 = _SIMD_LOAD(&q[(ldq*3)+3*offset]);
    __SIMD_DATATYPE a4_4 = _SIMD_LOAD(&q[(ldq*2)+3*offset]);
    __SIMD_DATATYPE a5_4 = _SIMD_LOAD(&q[(ldq)+3*offset]);
    __SIMD_DATATYPE a6_4 = _SIMD_LOAD(&q[3*offset]);

1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE t4 = _SIMD_FMA(a5_4, h_6_5, a6_4);
    t4 = _SIMD_FMA(a4_4, h_6_4, t4);
    t4 = _SIMD_FMA(a3_4, h_6_3, t4);
    t4 = _SIMD_FMA(a2_4, h_6_2, t4);
    t4 = _SIMD_FMA(a1_4, h_6_1, t4);
    register __SIMD_DATATYPE v4 = _SIMD_FMA(a4_4, h_5_4, a5_4);
    v4 = _SIMD_FMA(a3_4, h_5_3, v4);
    v4 = _SIMD_FMA(a2_4, h_5_2, v4);
    v4 = _SIMD_FMA(a1_4, h_5_1, v4);
    register __SIMD_DATATYPE w4 = _SIMD_FMA(a3_4, h_4_3, a4_4);
    w4 = _SIMD_FMA(a2_4, h_4_2, w4);
    w4 = _SIMD_FMA(a1_4, h_4_1, w4);
    register __SIMD_DATATYPE z4 = _SIMD_FMA(a2_4, h_3_2, a3_4);
    z4 = _SIMD_FMA(a1_4, h_3_1, z4);
    register __SIMD_DATATYPE y4 = _SIMD_FMA(a1_4, h_2_1, a2_4);
#else
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
    register __SIMD_DATATYPE t4 = _SIMD_ADD(a6_4, _SIMD_MUL(a5_4, h_6_5));
    t4 = _SIMD_ADD(t4, _SIMD_MUL(a4_4, h_6_4));
    t4 = _SIMD_ADD(t4, _SIMD_MUL(a3_4, h_6_3));
    t4 = _SIMD_ADD(t4, _SIMD_MUL(a2_4, h_6_2));
    t4 = _SIMD_ADD(t4, _SIMD_MUL(a1_4, h_6_1));
    register __SIMD_DATATYPE v4 = _SIMD_ADD(a5_4, _SIMD_MUL(a4_4, h_5_4));
    v4 = _SIMD_ADD(v4, _SIMD_MUL(a3_4, h_5_3));
    v4 = _SIMD_ADD(v4, _SIMD_MUL(a2_4, h_5_2));
    v4 = _SIMD_ADD(v4, _SIMD_MUL(a1_4, h_5_1));
    register __SIMD_DATATYPE w4 = _SIMD_ADD(a4_4, _SIMD_MUL(a3_4, h_4_3));
    w4 = _SIMD_ADD(w4, _SIMD_MUL(a2_4, h_4_2));
    w4 = _SIMD_ADD(w4, _SIMD_MUL(a1_4, h_4_1));
    register __SIMD_DATATYPE z4 = _SIMD_ADD(a3_4, _SIMD_MUL(a2_4, h_3_2));
    z4 = _SIMD_ADD(z4, _SIMD_MUL(a1_4, h_3_1));
    register __SIMD_DATATYPE y4 = _SIMD_ADD(a2_4, _SIMD_MUL(a1_4, h_2_1));
1744
#endif /* __ELPA_USE_FMA__ */
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754

    register __SIMD_DATATYPE x4 = a1_4;

    __SIMD_DATATYPE a1_5 = _SIMD_LOAD(&q[(ldq*5)+4*offset]);
    __SIMD_DATATYPE a2_5 = _SIMD_LOAD(&q[(ldq*4)+4*offset]);
    __SIMD_DATATYPE a3_5 = _SIMD_LOAD(&q[(ldq*3)+4*offset]);
    __SIMD_DATATYPE a4_5 = _SIMD_LOAD(&q[(ldq*2)+4*offset]);
    __SIMD_DATATYPE a5_5 = _SIMD_LOAD(&q[(ldq)+4*offset]);
    __SIMD_DATATYPE a6_5 = _SIMD_LOAD(&q[4*offset]);

1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE t5 = _SIMD_FMA(a5_5, h_6_5, a6_5);
    t5 = _SIMD_FMA(a4_5, h_6_4, t5);
    t5 = _SIMD_FMA(a3_5, h_6_3, t5);
    t5 = _SIMD_FMA(a2_5, h_6_2, t5);
    t5 = _SIMD_FMA(a1_5, h_6_1, t5);
    register __SIMD_DATATYPE v5 = _SIMD_FMA(a4_5, h_5_4, a5_5);
    v5 = _SIMD_FMA(a3_5, h_5_3, v5);
    v5 = _SIMD_FMA(a2_5, h_5_2, v5);
    v5 = _SIMD_FMA(a1_5, h_5_1, v5);
    register __SIMD_DATATYPE w5 = _SIMD_FMA(a3_5, h_4_3, a4_5);
    w5 = _SIMD_FMA(a2_5, h_4_2, w5);
    w5 = _SIMD_FMA(a1_5, h_4_1, w5);
    register __SIMD_DATATYPE z5 = _SIMD_FMA(a2_5, h_3_2, a3_5);
    z5 = _SIMD_FMA(a1_5, h_3_1, z5);
    register __SIMD_DATATYPE y5 = _SIMD_FMA(a1_5, h_2_1, a2_5);
#else
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
    register __SIMD_DATATYPE t5 = _SIMD_ADD(a6_5, _SIMD_MUL(a5_5, h_6_5));
    t5 = _SIMD_ADD(t5, _SIMD_MUL(a4_5, h_6_4));
    t5 = _SIMD_ADD(t5, _SIMD_MUL(a3_5, h_6_3));
    t5 = _SIMD_ADD(t5, _SIMD_MUL(a2_5, h_6_2));
    t5 = _SIMD_ADD(t5, _SIMD_MUL(a1_5, h_6_1));
    register __SIMD_DATATYPE v5 = _SIMD_ADD(a5_5, _SIMD_MUL(a4_5, h_5_4));
    v5 = _SIMD_ADD(v5, _SIMD_MUL(a3_5, h_5_3));
    v5 = _SIMD_ADD(v5, _SIMD_MUL(a2_5, h_5_2));
    v5 = _SIMD_ADD(v5, _SIMD_MUL(a1_5, h_5_1));
    register __SIMD_DATATYPE w5 = _SIMD_ADD(a4_5, _SIMD_MUL(a3_5, h_4_3));
    w5 = _SIMD_ADD(w5, _SIMD_MUL(a2_5, h_4_2));
    w5 = _SIMD_ADD(w5, _SIMD_MUL(a1_5, h_4_1));
    register __SIMD_DATATYPE z5 = _SIMD_ADD(a3_5, _SIMD_MUL(a2_5, h_3_2));
    z5 = _SIMD_ADD(z5, _SIMD_MUL(a1_5, h_3_1));
    register __SIMD_DATATYPE y5 = _SIMD_ADD(a2_5, _SIMD_MUL(a1_5, h_2_1));
1787
#endif /* __ELPA_USE_FMA__ */
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797

    register __SIMD_DATATYPE x5 = a1_5;

    __SIMD_DATATYPE a1_6 = _SIMD_LOAD(&q[(ldq*5)+5*offset]);
    __SIMD_DATATYPE a2_6 = _SIMD_LOAD(&q[(ldq*4)+5*offset]);
    __SIMD_DATATYPE a3_6 = _SIMD_LOAD(&q[(ldq*3)+5*offset]);
    __SIMD_DATATYPE a4_6 = _SIMD_LOAD(&q[(ldq*2)+5*offset]);
    __SIMD_DATATYPE a5_6 = _SIMD_LOAD(&q[(ldq)+5*offset]);
    __SIMD_DATATYPE a6_6 = _SIMD_LOAD(&q[5*offset]);

1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
#ifdef __ELPA_USE_FMA__
    register __SIMD_DATATYPE t6 = _SIMD_FMA(a5_6, h_6_5, a6_6);
    t6 = _SIMD_FMA(a4_6, h_6_4, t6);
    t6 = _SIMD_FMA(a3_6, h_6_3, t6);
    t6 = _SIMD_FMA(a2_6, h_6_2, t6);
    t6 = _SIMD_FMA(a1_6, h_6_1, t6);
    register __SIMD_DATATYPE v6 = _SIMD_FMA(a4_6, h_5_4, a5_6);
    v6 = _SIMD_FMA(a3_6, h_5_3, v6);
    v6 = _SIMD_FMA(a2_6, h_5_2, v6);
    v6 = _SIMD_FMA(a1_6, h_5_1, v6);
    register __SIMD_DATATYPE w6 = _SIMD_FMA(a3_6, h_4_3, a4_6);
    w6 = _SIMD_FMA(a2_6, h_4_2, w6);
    w6 = _SIMD_FMA(a1_6, h_4_1, w6);
    register __SIMD_DATATYPE z6 = _SIMD_FMA(a2_6, h_3_2, a3_6);
    z6 = _SIMD_FMA(a1_6, h_3_1, z6);
    register __SIMD_DATATYPE y6 = _SIMD_FMA(a1_6, h_2_1, a2_6);
#else
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
    register __SIMD_DATATYPE t6 = _SIMD_ADD(a6_6, _SIMD_MUL(a5_6, h_6_5));
    t6 = _SIMD_ADD(t6, _SIMD_MUL(a4_6, h_6_4));
    t6 = _SIMD_ADD(t6, _SIMD_MUL(a3_6, h_6_3));
    t6 = _SIMD_ADD(t6, _SIMD_MUL(a2_6, h_6_2));
    t6 = _SIMD_ADD(t6, _SIMD_MUL(a1_6, h_6_1));
    register __SIMD_DATATYPE v6 = _SIMD_ADD(a5_6, _SIMD_MUL(a4_6, h_5_4));
    v6 = _SIMD_ADD(v6, _SIMD_MUL(a3_6, h_5_3));
    v6 = _SIMD_ADD(v6, _SIMD_MUL(a2_6, h_5_2));
    v6 = _SIMD_ADD(v6, _SIMD_MUL(a1_6, h_5_1));
    register __SIMD_DATATYPE w6 = _SIMD_ADD(a4_6, _SIMD_MUL(a3_6, h_4_3));
    w6 = _SIMD_ADD(w6, _SIMD_MUL(a2_6, h_4_2));
    w6 = _SIMD_ADD(w6, _SIMD_MUL(a1_6, h_4_1));
    register __SIMD_DATATYPE z6 = _SIMD_ADD(a3_6, _SIMD_MUL(a2_6, h_3_2));
    z6 = _SIMD_ADD(z6, _SIMD_MUL(a1_6, h_3_1));
    register __SIMD_DATATYPE y6 = _SIMD_ADD(a2_6, _SIMD_MUL(a1_6, h_2_1));
1830
1831
#endif /* __ELPA_USE_FMA__ */
 
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
    register __SIMD_DATATYPE x6 = a1_6;

    __SIMD_DATATYPE q1;
    __SIMD_DATATYPE q2;
    __SIMD_DATATYPE q3;
    __SIMD_DATATYPE q4;
    __SIMD_DATATYPE q5;
    __SIMD_DATATYPE q6;

    __SIMD_DATATYPE h1;
    __SIMD_DATATYPE h2;
    __SIMD_DATATYPE h3;
    __SIMD_DATATYPE h4;
    __SIMD_DATATYPE h5;
    __SIMD_DATATYPE h6;
1847
1848
1849
1850
1851
1852

#endif /* BLOCK6 */


    for(i = BLOCK; i < nb; i++)
      {
1853
1854

#if VEC_SET == 128
1855
1856
1857
        h1 = _SSE_SET1(hh[i-(BLOCK-1)]);
        h2 = _SSE_SET1(hh[ldh+i-(BLOCK-2)]);
#endif
1858
#if VEC_SET == 1281
1859
1860
1861
        h1 = _SSE_SET(hh[i-(BLOCK-1)], hh[i-(BLOCK-1)]);
        h2 = _SSE_SET(hh[ldh+i-(BLOCK-2)], hh[ldh+i-(BLOCK-2)]);
#endif
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
#if  VEC_SET == 256
        h1 = _SIMD_BROADCAST(&hh[i-(BLOCK-1)]);
        h2 = _SIMD_BROADCAST(&hh[ldh+i-(BLOCK-2)]);
#endif /*   VEC_SET == 256 */

#ifdef __ELPA_USE_FMA__
        q1 = _SIMD_LOAD(&q[i*ldq]);
        x1 = _SIMD_FMA(q1, h1, x1);
        y1 = _SIMD_FMA(q1, h2, y1);
        q2 = _SIMD_LOAD(&q[(i*ldq)+offset]);
        x2 = _SIMD_FMA(q2, h1, x2);
        y2 = _SIMD_FMA(q2, h2, y2);
        q3 = _SIMD_LOAD(&q[(i*ldq)+2*offset]);
        x3 = _SIMD_FMA(q3, h1, x3);
        y3 = _SIMD_FMA(q3, h2, y3);
        q4 = _SIMD_LOAD(&q[(i*ldq)+3*offset]);
        x4 = _SIMD_FMA(q4, h1, x4);
        y4 = _SIMD_FMA(q4, h2, y4);
        q5 = _SIMD_LOAD(&q[(i*ldq)+4*offset]);
        x5 = _SIMD_FMA(q5, h1, x5);
        y5 = _SIMD_FMA(q5, h2, y5);
        q6 = _SIMD_LOAD(&q[(i*ldq)+5*offset]);
        x6 = _SIMD_FMA(q6, h1, x6);
        y6 = _SIMD_FMA(q6, h2, y6);
#else
        q1 = _SIMD_LOAD(&q[i*ldq]);
        x1 = _SIMD_ADD(x1, _SIMD_MUL(q1,h1));
        y1 = _SIMD_ADD(y1, _SIMD_MUL(q1,h2));
        q2 = _SIMD_LOAD(&q[(i*ldq)+offset]);
        x2 = _SIMD_ADD(x2, _SIMD_MUL(q2,h1));
        y2 = _SIMD_ADD(y2, _SIMD_MUL(q2,h2));
        q3 = _SIMD_LOAD(&q[(i*ldq)+2*offset]);
        x3 = _SIMD_ADD(x3, _SIMD_MUL(q3,h1));
        y3 = _SIMD_ADD(y3, _SIMD_MUL(q3,h2));
        q4 = _SIMD_LOAD(&q[(i*ldq)+3*offset]);
        x4 = _SIMD_ADD(x4, _SIMD_MUL(q4,h1));
        y4 = _SIMD_ADD(y4, _SIMD_MUL(q4,h2));
        q5 = _SIMD_LOAD(&q[(i*ldq)+4*offset]);
        x5 = _SIMD_ADD(x5, _SIMD_MUL(q5,h1));
        y5 = _SIMD_ADD(y5, _SIMD_MUL(q5,h2));
        q6 = _SIMD_LOAD(&q[(i*ldq)+5*offset]);
        x6 = _SIMD_ADD(x6, _SIMD_MUL(q6,h1));
        y6 = _SIMD_ADD(y6, _SIMD_MUL(q6,h2));
#endif /* __ELPA_USE_FMA__ */
1906
1907

#if defined(BLOCK4) || defined(BLOCK6)
1908
#if VEC_SET == 128
1909
1910
1911
        h3 = _SSE_SET1(hh[(ldh*2)+i-(BLOCK-3)]);
#endif

1912
#if VEC_SET == 1281
1913
1914