Update README.md

README.md

 # Firmware  project running in IPP-HGW on IPFN ATCA-MIMO-ISOL V2.1 Hardware Boards
 ## Xilinx Kintex 7 FPGA Module
- * [Trenz TE0741](https://wiki.trenz-electronic.de/display/PD/TE0741)
+ * The ATCA contains an FPGA plugin Module [Trenz TE0741](https://wiki.trenz-electronic.de/display/PD/TE0741)
 
 ## Getting started
 
-### Prerequisites
- * [Vivado Design Suite](https://www.xilinx.com/support/download.html)
- Master branch in currently using Vivado version 2019.2
+1.  Prerequisites
+ * The Master branch in currently using [Vivado Design Suite](https://www.xilinx.com/support/download.html),
+ version 2019.2, which needs a valid license to compile projects using Xilinx Kintex-7 XC7K325T FPGA
 
-### Checkout the latest release, and **cd** to the folder
-### Create and build the project in Vivado project Mode
+2.  Checkout the latest release, and `cd atca-mimo-v2-adc` to the folder
+3. Create and build the project in Vivado **Project Mode** (with GUI)
 
 Open Vivado IDE and do:
 ```
  Menu Tools->Run Tcl Script-> "scripts/project_create.tcl"
  You will need to (re-)generate IP cores in used in the Project, at least 
- PCIe endpoint
+ PCIe XDMA endpoint/DMA engine.
 
 ```
-Project files will be generated in `vivado_project`
+Project files will be generated in `vivado_project` folder
 
-### Build the project in Vivado non-Project Mode (CLI in Linux)
+4. (optional) Build the project in Vivado **non-Project Mode** (CLI in Linux)
 
-Open a console and Run:
+* Open a Linux console and Run:
 ```
  [~]source [...]/Xilinx/Vivado/2019.2/settings64.sh
  [~]time vivado -mode batch -source project_implement.tcl
@@ -31,16 +31,19 @@ Open a console and Run:
 
  Generated files will be in `out` folder.
 
- I should compile in ~ 10 minutes on a Intel i7 4-core Machine
+ The Project should compile in ~ 15 minutes on a Intel i7 4-core Machine.
 
-#### Program the FPGA (Kintex 7)
+5. Program the FPGA (Kintex 7) in **non-Project Mode**, for temporary testing.
 ```
  [~]vivado -mode batch -source scripts/program_fpga.tcl
 ```
-(You may need to change the reference to your JTAG programmer)
+* You may need to change the reference ID to your JTAG programmer. 
+* This may be well connected a remote machine running the Xilinx Hardware [Server](https://www.xilinx.com/member/forms/download/xef-vivado.html?filename=Xilinx_HW_Server_Lin_2019.2_1106_2127.tar.gz). 
+(You MUST use the same Vivado version!)
 
-#### Program the FPGA configuration Memory and reboot FPGA 
-Trenz Module has a SPI Memory type `s25fl256sxxxxxx0-spi-x1_x2_x4`
+6. Program the FPGA configuration Memory and reboot FPGA.
+* Note: Trenz Module has a SPI Memory type `s25fl256sxxxxxx0-spi-x1_x2_x4`
+* (optional) In **non-Project Mode**:
 
 ```
  [~] vivado -mode batch -source scripts/program_spi.tcl
@@ -48,21 +51,21 @@ Trenz Module has a SPI Memory type `s25fl256sxxxxxx0-spi-x1_x2_x4`
     
 ## Linux Device Drivers
 
-Driver code and tools were moved to a different git:
+* Driver code and tools in Master Branch were now moved to a different repository:
 
 https://gitlab.mpcdf.mpg.de/bcar/dma_ip_drivers
 
 (forked from )
-Xilinx github [xdma drivers](https://github.com/Xilinx/dma_ip_drivers "Xilinx Github")
+Xilinx github [xdma drivers](https://github.com/Xilinx/dma_ip_drivers) 
 
-Driver should compile in recent 4.x.y kernels
+* Driver should compile in recent 4.x.y kernels
 Go to `XDMA/linux-kernel/xdma`and run:
 - `make`
 
- Load driver in root mode with 
+ * Load driver in root mode with 
  - `#insmod adc_xdma.ko`
 
-Check driver loading with `dmesg`
+Check driver loading and troubleshoot with `dmesg`
 
 ### If you reprogram FPGA, driver should be reinstalled with:
 ```